Extended Gate Stack Structure for Parasitic Channel Suppression
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Solution Overview
Problem
As semiconductor devices continue to scale down, increased source/drain tunneling leads to higher leakage current and short channel effects, which can cause device failure. Additionally, parasitic channels formed under the gate stack and between source/drain regions act as leakage paths, impacting off-current and device performance.
Innovation Solution
The method involves forming an extended gate stack that extends into a region of the substrate with lower carrier mobility, reducing current leakage between source/drain regions. This is achieved by etching an opening from the upper substrate region to a lower region with lower carrier concentration, and forming the gate stack, including gate dielectric layers and gate electrodes, within this opening.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimensions of semiconductor devices are scaled down to increase storage capacity and processing speed, then device density and performance are improved, but source/drain tunneling increases leading to higher leakage current and short channel effects
Solution Approach 1:
The gate structure is extended from a conventional planar configuration into the third dimension by forming it within an opening that penetrates through the substrate. This vertical extension into the substrate creates an extended gate structure that provides better channel control and reduces short channel effects, thereby resolving the contradiction between device scaling and reliability.
Solution Approach 2:
The opening is etched into the substrate before the gate structure is formed, preparing the pathway in advance. This preliminary action allows the gate structure to be subsequently formed extending into the substrate, enabling improved electrical characteristics without compromising device density.
2Ease of manufacture
If conventional gate structures are used in scaled devices, then manufacturing simplicity is maintained, but parasitic channels formed under the gate stack create leakage paths that degrade device performance
Solution Approach 1:
The gate structure transitions from a surface-level planar configuration to a three-dimensional structure extending vertically into the substrate. This dimensional change eliminates the parasitic channel formation area under the gate stack by removing the substrate region beneath the gate, thereby preventing leakage paths while maintaining manufacturing feasibility through standard etching and deposition processes.
3Reliability
If the gate structure is extended into the substrate to reduce leakage, then short channel effects and subthreshold leakage are improved, but device structure complexity increases
Solution Approach 1:
The gate structure is segmented into distinct portions: a first portion formed between nanostructures and a second portion formed within the opening in the substrate. This segmentation allows the extended gate structure to be integrated systematically into the device, managing complexity through modular construction while achieving improved electrical characteristics.
Data Source
AI summary
The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes nanostructures on a substrate and a source/drain region in contact with the nanostructures. The semiconductor device also includes a gate structure that includes first and second portions. The first portion is formed between each nanostructure of nanostructures. The second portion is formed under the bottom-most nanostructure of the plurality of nanostructures and extends under a top surface of the substrate.