Offloading Computation via Extended ISA to Storage DPUs
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Solution Overview
Problem
The CPU-based model of calculation introduces significant drawbacks such as cache coherence issues, memory wall problems, and inefficient data movement, limiting improved computation performance for data processing.
Innovation Solution
Computation is offloaded to data storage space using an extended instructions set architecture (ISA), where data processing units (DPUs) in the storage device process data, bypassing CPU cores. This involves creating an extended ISA based on frequently executed functions, synthesizing code, and recompiling applications to execute extended instructions on storage device-side DPUs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If computation is performed using CPU-based model, then data processing can be executed, but cache coherence issues and memory wall problems occur leading to poor performance
Solution Approach 1:
The patent extracts computation tasks from the CPU-based model and relocates them to storage device-side DPUs. By taking out the computation function from the traditional CPU architecture and implementing it in storage devices, the system eliminates cache coherence issues and memory wall problems while maintaining data processing capabilities.
Solution Approach 2:
The patent segments the computation function into separate DPUs within storage devices, independent from the CPU. This segmentation allows computation to be performed locally at storage devices without requiring CPU intervention, thereby resolving cache coherence and memory wall issues while improving overall data processing performance.
2Productivity
If computation is offloaded to storage device DPUs, then data processing performance improves and power consumption decreases, but device complexity increases due to extended ISA requirements
Solution Approach 1:
The patent implements a universal extended ISA that enables both CPU and storage device DPUs to execute the same instruction set. This multi-functionality allows the storage device to perform computation tasks originally requiring CPU involvement, improving data processing performance while managing complexity through a unified instruction architecture.
Solution Approach 2:
The patent changes the execution location parameter from CPU to storage device DPU by introducing extended ISA instructions. This parameter change enables computation to be offloaded to storage devices, improving performance and reducing power consumption consumed by CPU while the complexity is managed through standardized instruction extensions.
3Productivity
If traditional CPU-based computation is used, then applications can be executed, but data movement efficiency is poor and power consumption is high
Solution Approach 1:
The patent extracts computation functions from the CPU and implements them directly in storage devices. By taking out the computation task from the traditional CPU architecture and placing it in storage devices, the system reduces data movement distance and power consumption while improving data processing throughput.
Solution Approach 2:
The patent enables storage devices to perform computation tasks independently using extended ISA instructions. This self-service capability allows storage devices to process data locally without requiring continuous CPU intervention or extensive data movement, thereby reducing power consumption while maintaining high processing throughput.
Data Source
AI summary
The present disclosure describes techniques for offloading computation based on an extended instruction set architecture (ISA). The extended ISA may be created based on identifying functions executed multiple times by a central processing unit (CPU). The extended ISA may comprise hashes corresponding to the functions and identifiers of extended operations associated with the functions. The extended operations may be converted from original operations of the functions. The extended operations may be executable by a storage device. The storage device may be associated with at least one computational core. Code may be synthesized based at least in part on the extended ISA. Computation of the synthesized code may be offloaded into the storage device.