Extended Isomorphism Compiler Vectorization
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Solution Overview
Problem
Conventional compiler-based automatic vectorization techniques, such as Superword Level Parallelism (SLP), face challenges in efficiently utilizing SIMD capabilities due to non-consecutive memory accesses, which limit the effectiveness of vectorization and increase operational costs, especially in the presence of control flow and non-consecutive memory layouts.
Innovation Solution
The method identifies partial-isomorphic statements with equivalent operations but non-consecutive memory accesses, analyzes their actual memory layout, and sorts them to appear consecutive, marking them as extended-isomorphic, allowing for sequential physical memory accesses and improved vectorization opportunities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional SLP vectorization is applied to scalar code, then vector instructions are generated, but non-consecutive memory accesses reduce effectiveness and increase operational costs
Solution Approach 1:
The patent performs preliminary analysis of memory access patterns during compilation to identify partial-isomorphic statements with non-consecutive accesses. By detecting these patterns before code generation and applying reordering transformations, the compiler prepares the code structure in advance to enable effective vectorization, rather than attempting to vectorize non-consecutive accesses directly
Solution Approach 2:
The patent changes the parameter of memory access consecutiveness by reordering statements to transform non-consecutive accesses into consecutive ones. This parameter transformation allows the vectorizer to effectively process the code, converting operational expenses into performance benefits through extended isomorphism detection
2Productivity
If packing and unpacking techniques are used to handle non-consecutive memory accesses, then vectorization is enabled, but operational expenses increase
Solution Approach 1:
The patent performs preliminary detection and reordering of memory access patterns during compilation, transforming non-consecutive accesses into consecutive ones before vectorization. This preliminary preparation eliminates the need for complex packing and unpacking instructions, reducing instruction complexity while maintaining SIMD capability utilization
Solution Approach 2:
The patent extracts and handles the non-consecutive memory access pattern as a separate detectable feature during compilation. By identifying and reordering these specific access patterns in advance, the complex packing/unpacking operations are eliminated, leaving only simple consecutive vectorized instructions
3Ease of operation
If memory accesses are kept scalar to handle non-consecutive patterns, then operational simplicity is maintained, but SIMD capabilities are not utilized
Solution Approach 1:
The patent changes the parameter of access pattern consecutiveness through reordering, transforming scalar-friendly non-consecutive patterns into vector-friendly consecutive patterns. This parameter transformation enables the use of SIMD instructions while maintaining operational simplicity, achieving both ease of operation and improved processing speed
Data Source
AI summary
A method and apparatus provides for compiling a computer-readable computer program having a plurality of computer-readable statements into a plurality of computer-executable instructions. In one example, the method and apparatus determines when at least one pair of the computer-readable statements is partial-isomorphic having an equivalent operation and same order of operation but causing non-consecutive memory accesses, and generates the computer-executable instructions causing the at least one pair of the partial-isomorphic statements to perform sequential physical memory accesses.