Extended JTAG Controller for IC Reset and Power Reduction
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Solution Overview
Problem
The standardized procedure for testing integrated circuits (ICs) faces high power dissipation issues due to dynamic and leakage power consumption, which is a challenge for ultra-low power ICs.
Innovation Solution
An extended Joint Test Action Group (JTAG) controller is introduced, incorporating an overall reset generator controlled by a finite state machine, which simplifies the clock/reset modules by merging the design for testing infrastructure with the reset generator, allowing simultaneous use of all scan chains and eliminating the need for dedicated reset/set pins, thereby reducing power dissipation and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated reset modules are used for each digital unit, then reset functionality is ensured, but power dissipation increases and area is consumed
Solution Approach 1:
The patent merges the reset generator functionality into the JTAG controller by adding a reset output unit to the existing JTAG controller structure. This consolidation eliminates dedicated reset modules for each digital unit, reducing overall power dissipation while maintaining reset functionality through the shared JTAG controller resource.
Solution Approach 2:
The JTAG controller is extended to serve multiple functions: it maintains its original design-for-testing capabilities while simultaneously providing reset functionality to all digital units through the added reset output unit. This multi-functionality eliminates the need for separate dedicated reset modules, reducing both power consumption and area.
2Reliability
If dedicated reset modules are used for each digital unit, then reset functionality is ensured, but area is consumed
Solution Approach 1:
The patent merges the reset generator functionality into the JTAG controller by adding a reset output unit to the existing JTAG controller structure. This consolidation eliminates dedicated reset modules for each digital unit, reducing overall power dissipation while maintaining reset functionality through the shared JTAG controller resource.
Solution Approach 2:
The JTAG controller is extended to serve multiple functions: it maintains its original design-for-testing capabilities while simultaneously providing reset functionality to all digital units through the added reset output unit. This multi-functionality eliminates the need for separate dedicated reset modules, reducing both power consumption and area.
3Adaptability or versatility
If separate clock/reset modules are used, then functionality is complete, but device complexity increases
Solution Approach 1:
The patent merges the reset generator functionality into the JTAG controller by adding a reset output unit to the existing JTAG controller structure. This consolidation eliminates dedicated reset modules for each digital unit, reducing overall power dissipation while maintaining reset functionality through the shared JTAG controller resource.
Data Source
AI summary
An extended joint test action group based controller and a method of use allows easier testing of integrated circuits by reducing the power dissipation of an IC. The extended joint test action group (JTAG) controller tests internal storage elements that form digital units in an integrated circuit (IC) use a design for testing scan infrastructure on the IC, wherein the JTAG controller is extended by an overall reset generator for all digital units of the IC, and a finite state machine controls the overall reset generator. In reset mode the JTAG controller stops the at least one clock module in supplying the digital units that should be reset. It then sets all scan chains in test mode and switches the input multiplexers into reset mode; and then controls the number of shift clock cycles for shifting in the reset value to the flip-flops in the scan chain, respectively.