Extended Memory Architecture Single-Command Operations
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Solution Overview
Problem
As the size and quantity of data stored in memory devices increase, transferring data to and from a host becomes time-consuming and resource-intensive, leading to increased processing time and resource consumption, particularly when performing memory operations on large blocks of data.
Innovation Solution
The implementation of an extended memory architecture that allows for the performance of memory operations within computing devices using a single address and operand, reducing the need for multiple function calls and commands, and enabling data transfer through specialized communication subsystems like PCIe and AXI interconnects, which bypasses or minimizes the need to pass data through multiple computing devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred through multiple computing devices to perform memory operations, then data processing can be distributed and scalable, but processing time and resource consumption increase significantly
Solution Approach 1:
The patent extracts the memory operation capability from the host processor and places it directly in the memory device. This allows memory operations to be performed at the memory device level without requiring data to be transferred through multiple computing devices, thereby reducing processing time and resource consumption while maintaining distributed processing benefits
Solution Approach 2:
The patent introduces an extended memory architecture that acts as an intermediary between the host processor and traditional memory devices. This intermediary layer provides memory operation capabilities locally at the memory device, eliminating the need for complex data movement through multiple computing devices while maintaining system scalability
2Ease of operation
If multiple function calls and commands are used to perform memory operations on large data blocks, then operations can be broken down into manageable steps, but the number of commands increases processing overhead
Solution Approach 1:
The patent merges multiple memory operation commands into a single unified command structure. Instead of requiring separate function calls for each memory operation step, the extended memory architecture accepts a single command that performs the entire memory operation on large data blocks, significantly reducing command execution time and overhead while maintaining operational control
3Reliability
If data is transferred frequently between memory devices and host, then data can be kept synchronized and accessible, but transfer operations consume significant resources and time
Solution Approach 1:
The patent implements preliminary action by performing memory operations directly at the memory device before data transfer to the host is required. This allows data processing to be completed in advance at the source, reducing the frequency and volume of data transfers between memory devices and host, thereby conserving energy and time while maintaining data accessibility and synchronization
Data Source
AI summary
Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit configured to perform an operation on a block of data, and a memory array configured as a cache for each respective processing unit. The example apparatus can further include a first communication subsystem coupled to a host and to each of the plurality of communication subsystems. The example apparatus can further include a plurality of second communication subsystems coupled to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, send a command to execute at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.