Extended Packet Processing Pipeline for Flow Table Entry Management
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Solution Overview
Problem
Network appliances such as switches and routers face challenges in adapting to changing feature sets, protocols, and hardware configurations, with existing solutions like fixed function ASICs providing high-speed packet processing but lacking flexibility, and FPGAs offering flexibility at a high cost and power consumption.
Innovation Solution
Implementing an extended packet processing pipeline that offloads tasks from CPU cores to a specialized circuit, allowing for rapid search of flow table entries and reducing memory locking, thereby enhancing throughput and connection processing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If fixed function ASICs are used for packet processing, then high-speed processing is achieved, but flexibility to adapt to changing feature sets and protocols is lost
Solution Approach 1:
The patent implements a dynamically reconfigurable packet processing pipeline using P4 programming that allows the network appliance to adapt its processing logic in real-time. The pipeline can be programmed to handle different protocols, features, and hardware configurations without requiring physical reconfiguration, thus achieving both high-speed processing and adaptability. The system transitions from static fixed-function logic to dynamic programmable logic that can be updated via software.
2Adaptability or versatility
If FPGAs are used to provide flexibility, then adaptability to changing configurations is improved, but cost and power consumption increase significantly
Solution Approach 1:
The patent employs a cost-effective approach by using programmable logic that can be updated via software rather than expensive FPGAs. The system uses standard network appliance hardware with P4-programmable pipelines that provide the necessary flexibility at a fraction of the cost and power consumption of FPGAs. The solution replaces expensive reconfigurable hardware with more efficient software-defined processing.
3Adaptability or versatility
If CPU cores are used for flow table entry search, then configuration flexibility is maintained, but throughput decreases due to memory locking
Solution Approach 1:
The patent extracts the flow table search function from the CPU cores and implements it in dedicated hardware within the packet processing pipeline. This separation allows the CPU to focus on configuration tasks while the hardware pipeline handles high-speed packet processing and flow table lookups without causing memory bottlenecks. The search functionality is removed from the general-purpose CPU and placed in specialized processing units.
Solution Approach 2:
The patent introduces an intermediary mechanism where the P4-programmable pipeline acts as a bridge between the CPU and the packet processing function. The pipeline can be programmed to perform flow table searches independently, reducing the need for CPU intervention and memory locking. This intermediary layer enables parallel processing where the CPU configures the pipeline while the pipeline autonomously handles packet processing and flow table operations.
Data Source
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AI summary
A network appliance can be configured for storing a plurality of flow table entries in a flow table of a match-action pipeline, wherein the match-action pipeline is implemented via a packet processing circuit configured to process a plurality of network traffic flows associated with the plurality of flow table entries. An extended packet processing pipeline of the network appliance can read a flow table entry of the flow table. The extended packet processing pipeline can be implemented via a pipeline circuit. The extended packet processing pipeline can determine that a network traffic flow associated with the flow table entry is expired or terminated. The network appliance can delete the flow table entry from the flow table by processing a traffic flow deletion operation after determining that the network traffic flow is expired or terminated.