Extended Raised Source/Drain Structure for Contact Reliability
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Solution Overview
Problem
As integrated circuit dimensions shrink, making electrical and mechanical contact with Raised Source/Drain (RSD) regions in FET devices becomes increasingly difficult due to the presence of sidewall spacers, leading to partial or total connection with dielectric materials instead of conductive surfaces, resulting in high junction leakage and contact resistance issues.
Innovation Solution
The implementation of conformal L-shaped etch-stop layers with a vertical and horizontal leg, allowing for the formation of RSD regions that cover the etch-stop layers and provide a larger footprint for connections, reducing the risk of overetching and improving contact quality by ensuring connections are made to the conductive RSD regions rather than dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional sidewall spacers are used to define RSD regions, then manufacturing precision is improved, but contact reliability deteriorates due to reduced contact area and risk of contacting dielectric materials
Solution Approach 1:
The patent extends the RSD structure vertically to create an elevated platform, adding a height dimension to the contact structure. This vertical extension provides a larger contact footprint without increasing lateral dimensions, allowing reliable contact while maintaining precise lateral definition provided by sidewall spacers.
Solution Approach 2:
The patent forms the elevated RSD platform before making contact openings, ensuring that the contact structure has a predetermined enlarged footprint. This preliminary creation of the elevated structure prevents contact reliability issues before they can occur during subsequent processing steps.
2Productivity
If device dimensions are reduced to continue scaling, then productivity is improved, but contact reliability deteriorates due to increasingly difficult contact formation
Solution Approach 1:
By transitioning from a two-dimensional contact footprint to a three-dimensional elevated platform, the patent enables continued device scaling while maintaining adequate contact area. The vertical dimension compensates for reduced lateral dimensions, allowing smaller devices to achieve the same contact reliability as larger devices.
Solution Approach 2:
The patent changes the geometric parameters of the RSD structure by creating an elevated platform with increased height, thereby increasing the contact footprint volume and surface area available for contact formation, which compensates for overall device size reduction.
3Reliability
If via holes are etched to connect to RSD regions, then electrical connection is achieved, but junction leakage increases due to potential contact with lateral dielectric materials
Solution Approach 1:
The elevated RSD platform creates a vertical offset between the contact opening and the lateral dielectric materials. This height difference ensures that etched via holes contact the conductive RSD platform before reaching lateral dielectric regions, preventing junction leakage while achieving electrical connection.
Solution Approach 2:
The elevated RSD platform acts as an intermediary structure between the contact opening and the underlying active region. It provides a conductive interface that ensures proper electrical connection while physically separating the contact path from lateral dielectric materials that could cause leakage.
Data Source
AI summary
A semiconductor device comprises a gate electrode stack having sidewalls and a top surface with a gate dielectric layer and the gate electrode, and LDD/LDS regions in the substrate aligned with the stack. Conformal L-shaped etch-stop layers with a thickness from about 50 Å to about 200 Å are formed with a vertical leg on the sidewalls of the stack and a horizontal leg reaching over the LDD/LDS regions next to the stack. RSD regions are formed in contact with the substrate aside from the etch-stop layers. The RSD regions cover the horizontal leg of the etch-stop layer and cover at least a portion of the vertical leg of the etch-stop layer on the sidewall of the gate electrode.


