Extended Redistribution Layer Bumped Wafer I/O Density
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Solution Overview
Problem
Bumped die configurations in wafer-level packaging face limitations in increasing input/output (I/O) capability per specific area due to restricted space for bump deposition.
Innovation Solution
The method involves forming an insulating layer around semiconductor die, followed by a conductive layer and under bump metallization (UBM), with organic material deposition to expand the surface area for additional bump placement, thereby increasing I/O capacity without using additional wafer material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional bump technology is used on wafer, then I/O capability can be provided, but the area available for bump deposition is limited
Solution Approach 1:
The patent extends the bump deposition area from the traditional two-dimensional wafer surface to the three-dimensional side walls of the wafer. By forming organic material layers and conductive layers on the side walls, the invention creates additional deposition surfaces that increase the total area available for bump placement without requiring additional wafer material.
Solution Approach 2:
The invention segments the bump deposition locations into multiple regions: traditional top surface areas and newly created side wall areas. This segmentation allows bumps to be distributed across different spatial zones, effectively increasing the total I/O capability while utilizing both the original wafer surface and the extended side wall surfaces.
2Quantity of substance
If more bumps are placed on the chip surface to increase I/O capacity, then thermal management improves, but the specific area for bump placement becomes insufficient
Solution Approach 1:
The patent resolves this contradiction by transitioning from two-dimensional surface utilization to three-dimensional structure utilization. The side walls of the wafer are converted into active bump deposition surfaces through the formation of organic material layers and conductive layers, thereby expanding the total available area for thermal management bumps without increasing the chip's footprint.
3Quantity of substance
If wafer material is used to expand surface area for additional bumps, then I/O capacity increases, but wafer yield decreases
Solution Approach 1:
The patent employs composite material structures consisting of organic material layers (such as benzocyclobutene or polyimide) combined with conductive layers on the side walls. This composite approach creates functional deposition surfaces that increase I/O capacity without consuming additional wafer material, thereby maintaining wafer yield while achieving higher bump density.
Data Source
AI summary
A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad.