Extended Scan Flip-Flops for High-Coverage Circuit Testing
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Solution Overview
Problem
Integrated circuits, such as microcontrollers, require high test coverage but adding additional flip-flops for observation points increases cost and chip size, making it undesirable.
Innovation Solution
Implementing extended scan flip-flops with additional input circuitry to function as both input wrapper cells and observation points, reducing the need for dedicated observation points and minimizing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional flip-flops are added to implement observation points for high test coverage, then test coverage is improved, but chip cost and size increase
Solution Approach 1:
The scan flip-flops are designed to perform dual functions: serving as input wrapper cells during normal operation and as observation points during testing. The test input circuit includes a multiplexer that can switch between receiving data from the preceding flip-flop in the sequence or from a test result signal, enabling the same hardware to support both operational and testing requirements without adding dedicated observation point flip-flops.
2Reliability
If additional flip-flops are added to implement observation points for high test coverage, then test coverage is improved, but chip cost increases
Solution Approach 1:
The scan flip-flops are designed to perform dual functions: serving as input wrapper cells during normal operation and as observation points during testing. The test input circuit includes a multiplexer that can switch between receiving data from the preceding flip-flop in the sequence or from a test result signal, enabling the same hardware to support both operational and testing requirements without adding dedicated observation point flip-flops.
3Area of stationary object
If scan flip-flops are extended with additional input circuitry to function as both input wrapper cells and observation points, then chip area is reduced, but device complexity increases
Solution Approach 1:
A test input circuit is introduced as an intermediary component between the sequential input wrapper scan flip-flops and the test result output. This circuit includes a multiplexer that mediates the signal flow by selecting whether to capture data from the preceding flip-flop or from the test result signal, thereby managing the added complexity in a controlled manner while achieving the goal of reduced chip area.
Data Source
AI summary
According to various embodiments, a circuit is described including a plurality of scan flip-flops including a sequence of input wrapper scan flip-flops and including, for each input wrapper scan flip-flop of at least a subset of the input wrapper scan flip-flops, at the input wrapper scan flip-flop's test input a respective test input circuit configured to, when supplied with a mode control signal having a first value, connect the test input to the output of the preceding input wrapper scan flip-flop such that the test input of the flip-flop is supplied with the content of the preceding input wrapper scan flip-flop and when supplied with the mode control signal having a second value, connect the test input to an output of a part of the circuit such that the test input of the flip-flop is supplied with a value depending on a test result.


