Extended Backside Source/Drain Contact for Low-Resistance Power Rails
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Solution Overview
Problem
Conventional semiconductor device backside contact structures face increased contact resistance due to direct source/drain (S/D) backside contact and clock signal backside contact proximity, leading to potential VDD/VSS shorting with the clock signal line.
Innovation Solution
The implementation of a direct backside contact between a source or drain line and its respective region, with a clock signal line contact via connected to the gate, surrounded by deep shallow trench isolation (STI) fill to prevent shorting, and an extension at the contact end to enhance the contact surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If direct backside contact is implemented between source/drain lines and regions, then contact resistance is reduced, but risk of shorting between power lines and clock signal lines increases
Solution Approach 1:
A deep shallow trench isolation (STI) fill structure is introduced as an intermediary element between the backside power distribution network and clock signal contact vias. This deep STI fill extends deeper than conventional STI structures, creating physical separation and preventing direct contact between power lines and clock signal lines, thereby eliminating the shorting risk while preserving low contact resistance pathways.
Solution Approach 2:
The isolation structure is extended into the vertical dimension (depth) rather than relying solely on lateral separation. By deepening the STI fill to extend below the clock signal contact via level, the design creates three-dimensional separation that prevents shorting while maintaining effective two-dimensional contact areas for power distribution.
2Productivity
If direct backside contact is implemented, then power distribution efficiency is improved, but contact area between power lines and regions is insufficient
Solution Approach 1:
The contact structure transitions from a two-dimensional planar contact to a three-dimensional extended contact by forming the deep STI fill that protrudes upward. This vertical extension effectively increases the contact surface area between power lines and active regions without expanding the lateral footprint, thereby improving power distribution efficiency while maintaining compact device geometry.
Data Source
AI summary
A semiconductor device includes at least a direct backside contact between a source line and a source epitaxial growth and/or a drain line and a drain epitaxial growth. A clock signal line contact via can connect a gate to a backside clock signal line. The clock signal line contact via is surrounded by a deep STI fill to prevent shorting between the clock signal line and the source and/or drain lines in the backside power rail.