Extended Source-Drain Contacts Reduce Parasitic Resistance
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Solution Overview
Problem
Advanced deep sub-micron semiconductor fabrication processes face increased parasitic resistance in metal routing structures, leading to higher IR drops and reduced voltage headroom, which complicates the design of low-impedance I/O drivers and is exacerbated by the difficulty in accommodating additional vias due to high metal routing density and chip layout design rule constraints.
Innovation Solution
The solution involves extending the length of source/drain contacts beyond the active region of transistors to increase contact area, allowing additional vias to be placed without violating design rules, thereby reducing parasitic resistance through the use of extended source/drain contacts and additional vias within the contact areas, which are strategically positioned to connect with metal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional vias are added to reduce parasitic resistance, then parasitic resistance decreases, but metal routing density increases and design rule violations occur
Solution Approach 1:
The source/drain contact is extended in the lateral dimension beyond the active region boundaries. This dimensional extension provides additional space in the metal routing layer to place vias without increasing vertical routing density or violating design rules. The extended contact creates a larger footprint area where vias can be strategically positioned to reduce parasitic resistance while maintaining acceptable metal routing density.
2Reliability
If source/drain contact area is increased to accommodate more vias, then parasitic resistance reduces, but chip area increases
Solution Approach 1:
The source/drain contact is extended only in specific local regions where via placement is needed, rather than uniformly increasing the entire contact area. The extension is strategically positioned beyond the active region boundaries to provide via placement space while minimizing the overall area penalty. This localized extension approach reduces parasitic resistance through additional vias without significantly increasing total chip area.
3Productivity
If metal routing structures are scaled down to maintain geometry, then device density increases, but parasitic resistance increases
Solution Approach 1:
As metal routing structures are scaled down in vertical and lateral dimensions to maintain device density, the source/drain contact is extended in the lateral dimension to compensate for the reduced via capacity. This dimensional extension provides additional space to place vias that can carry current, thereby maintaining acceptable parasitic resistance levels despite the scaled-down metal routing structures and increased device density.
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
In certain aspects of the disclosure, a die includes one or more fins, a gate formed over a first portion of the one or more fins, and a first source/drain contact formed over a second portion of the one or more fins, wherein the first source/drain contact includes an extended portion that does not overlap the one or more fins. The die also includes first and second metal lines formed from a first metal layer, wherein the first and second metal lines are spaced apart. The die further includes a first via connecting the first source/drain contact to the first metal line, and a second via connecting the first source/drain contact to the second metal line, wherein the second via lies within the extended portion of the first source/drain contact.