Extended Transistor Geometry Cell Layout for Mixed-Height Logic Rows
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Solution Overview
Problem
Existing digital design tools are limited in their ability to efficiently use logic cells of varying heights and performance levels within a single circuit design, leading to wasted area due to the use of higher performance cells where lower performance cells suffice.
Innovation Solution
The integration of multiple logic cells with different heights and performance levels, where a first row of logic cells with a lower drive strength is paired with an extension logic cell in a second row, allowing the extension logic cell to occupy unused space in the first row and extend into the second row, thereby optimizing area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If logic cells of varying heights and performance levels are integrated into a single circuit design, then area efficiency is improved, but design complexity increases
Solution Approach 1:
The logic cell is segmented into two distinct parts: a first logic portion occupying a first row and a second logic portion occupying a second row. This segmentation allows each portion to be independently designed and optimized for specific performance requirements while maintaining overall cell functionality.
Solution Approach 2:
Different portions of the logic cell are assigned different heights and performance characteristics based on local requirements. The first logic portion has a first height suitable for its function, while the second logic portion has a second height optimized for its specific needs, allowing area efficiency without uniform high-performance design throughout.
2Speed
If higher performance logic cells are used throughout the design, then propagation delay is reduced, but area waste increases
Solution Approach 1:
The logic cell implements different performance levels in different portions: the first logic portion operates at a first performance level optimized for its specific function, while the second logic portion operates at a second performance level. This allows high performance where needed without paying the area penalty throughout the entire cell.
Solution Approach 2:
Rather than designing the entire logic cell for maximum performance, only the portions that require high speed operation are designed with corresponding performance characteristics. Other portions use optimized-but-not-maximal performance designs, reducing overall area while maintaining necessary speed for critical paths.
3Area of stationary object
If logic cells with different heights are used, then area optimization is achieved, but manufacturing complexity increases
Solution Approach 1:
The logic cell is divided into two vertically separated portions occupying different rows, with power rails positioned between them. This segmentation into standardized row-based units facilitates manufacturing by allowing each portion to be processed and connected using standard fabrication techniques.
Solution Approach 2:
Power rails serve as intermediary structures positioned between the first and second logic portions. These power rails provide both electrical connectivity and structural organization, simplifying the manufacturing process by establishing clear connection points and voltage domains between the different-height portions.
Data Source
AI summary
An IC includes first-third power rails over a semiconductor substrate. The first rail has a first polarity different from the second and third rails. The IC includes multiple first cells on the semiconductor substrate in first and second rows. The first row is separated from the second row by the first power rail. Each first cell includes a first height and a first structure having at least one transistor. For each first cell in the first row, the first structure is entirely between the first and second rails. Further, for each first cell in the second row, the first structure is between the first and third rails. The IC includes an extension cell arranged on the semiconductor substrate in the first row. The extension cell includes a second structure having at least one transistor. A portion of the second structure extends into the second row.