Extended TSV Power Delivery in Face-to-Face Die Stacks
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Solution Overview
Problem
Forming semiconductor devices from multiple dies poses challenges due to high connection resistance, inductive and capacitive effects, and reduced yields, especially in face-to-face arrangements where power delivery is limited by resistive paths through thin metallization layers and vias, and interference from adjacent dies degrades inductor performance.
Innovation Solution
Extending Through Silicon Vias (TSVs) through at least one metallization layer of a semiconductor die to connect to a thicker metallization layer for enhanced power delivery, and forming probe pads for individual die testing to increase yields, while creating voids to reduce parasitic capacitance around inductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If power is delivered through traditional TSVs and thin metallization layers in face-to-face die arrangement, then interconnect density is high, but power delivery capability is insufficient due to high resistance
Solution Approach 1:
The patent extends TSVs vertically through the entire die stack and introduces horizontal power delivery paths using thicker metallization layers (e.g., M5-M7 layers) to create a three-dimensional power distribution network. This multi-dimensional approach allows power to be delivered through both vertical (TSV) and horizontal (metallization) paths, reducing overall resistance while maintaining high interconnect density.
Solution Approach 2:
The patent creates a composite power delivery structure combining TSVs (vertical interconnects) with thicker metallization layers (horizontal conductors). This composite structure leverages the advantages of both components: TSVs provide vertical connectivity while thicker metallization layers provide low-resistance horizontal power distribution, together forming a robust power delivery system.
2Length of moving object
If all signals are communicated between dies using TSVs extending through the entire bottom die, then connection path length is reduced, but TSV size increases resulting in lower interconnect density
Solution Approach 1:
The patent segments the power and signal communication paths by using different TSV configurations for different functions. Some TSVs extend through the entire die stack for vertical communication, while other interconnects use lateral metallization paths. This segmentation allows optimization of each path type, maintaining short connection lengths while preserving high interconnect density.
3Strength
If microbumps with underfill are used to connect dies, then mechanical bonding is achieved, but thermal performance is compromised
Solution Approach 1:
The patent extracts the underfill material from the bonding interface, using direct microbump-to-microbump bonding without underfill. This elimination of underfill removes the thermal barrier, allowing efficient heat dissipation through the bonding interface while maintaining mechanical strength through proper microbump design and arrangement.
Data Source
AI summary
A TSV of a first semiconductor die may extend from a semiconductor substrate of the first semiconductor die through at least one metallization layer of the die to connect to a metallization layer to supply power to the second semiconductor die. By extending the TSV, resistance may be reduced, allowing for enhanced power delivery to the second semiconductor die. Resistance may be further reduced by allowing for the TSV to connect to a thicker metallization layer than would otherwise be possible. Also, in some embodiments, the TSV may connect to a metallization layer that is suitable for supplying power to both semiconductor dies. The first semiconductor die may be a top die or a bottom die in a face-to-face arrangement. Disclosed concepts may be extended to any number of dies included in a die stack that includes the face-to-face arrangement.