Extended Valid Address Window in Double Pumped Memory
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Solution Overview
Problem
In double pumped address scheme memory devices, the valid address window becomes narrower as the operating frequency increases, leading to an insufficient margin between internal address signals and command signals, which affects the stable generation of row and column addresses.
Innovation Solution
A memory device and method that extend the valid address window by generating extended internal address signals, using a valid command signal generator, address buffer, command buffer, and address latch circuit to ensure a valid window of at least two clock cycles, thereby securing a sufficient margin for latching internal address signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating frequency is increased, then the productivity is improved, but the valid address window becomes narrower
Solution Approach 1:
The patent applies preliminary action by generating extended internal address signals in advance before the command signal is fully processed. The address buffer generates extended first and second internal address signals based on preliminary internal address signals, creating a head start that extends the valid address window duration to accommodate higher operating frequencies while maintaining signal stability and timing margins.
2Productivity
If the operating frequency is increased, then the productivity is improved, but the margin between internal address signals and command signals becomes insufficient
Solution Approach 1:
The address buffer generates extended internal address signals in advance before the command signal processing completes. By creating these extended signals preliminarily, the patent establishes a time margin that ensures reliable signal timing even at higher operating frequencies where the conventional valid address window would be too narrow.
Solution Approach 2:
The patent extends the valid address window by adding a temporal dimension to the signal generation process. Instead of relying solely on the conventional single-cycle window, the address buffer creates extended signals that span multiple clock cycles, effectively adding time dimension to the address signal validity period and thereby increasing the margin between signals.
3Reliability
If the valid address window is extended, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The address buffer is segmented into functional components: an input buffer for receiving address signals, a sampler for capturing signals at specific clock edges, and a delay element for timing control. This segmentation allows the complex function of extending the valid address window to be broken down into manageable sub-functions, making the design more systematic and easier to implement.
Solution Approach 2:
The address buffer acts as an intermediary component between the external address signals and the internal command signal processing. It receives preliminary internal address signals, generates extended versions of them, and provides these extended signals to the address latch circuit. This intermediary function simplifies the overall system by centralizing the signal extension logic in a dedicated buffer module.
Data Source
AI summary
Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.