Extended Vector Registers for Matrix Multiplication Performance
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Solution Overview
Problem
Current vector processors face limitations in efficiently executing matrix multiplications due to insufficient vector register width and memory bandwidth, which restricts performance and flexibility, especially for applications requiring large data sets.
Innovation Solution
The introduction of extended vector registers and functional units that allow for customizable configurations, enabling wider vector operations and improved memory management through a processor architecture that supports static instruction scheduling with a time counter, allowing for out-of-order execution and optimized resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vector register width is increased to handle large matrix multiplications, then performance for matrix multiplication improves, but device complexity and area increase
Solution Approach 1:
The vector register file is segmented into multiple sub-registers (first vector register and second vector register) that can be independently accessed. This allows the system to achieve effective wide register width for matrix multiplication while maintaining manageable complexity through modular organization of register segments.
Solution Approach 2:
The patent introduces a register bank dimension with multiple register files (first vector register file, second vector register file, third vector register file) that can be selectively accessed. This dimensional expansion allows the system to provide extended register width capability without physically implementing a single monolithic wide register, thereby reducing complexity.
2Productivity
If vector functional unit width is increased to match extended register width, then performance improves, but device complexity and cost increase
Solution Approach 1:
The vector functional unit operates with a fixed width that is sufficient for many applications, while the register files provide extended width capability when needed. This partial action approach allows the functional unit to remain simpler while the register system provides enhanced capability through software configuration and selective access to extended registers.
Solution Approach 2:
The vector functional unit is designed to work with both the standard vector register width and the extended register width through software control. The same functional unit can serve multiple purposes by accessing different register files, eliminating the need for separate functional units for different width operations.
3Productivity
If vector register width is extended to store large matrices, then memory bandwidth requirements are reduced, but area and power consumption increase
Solution Approach 1:
The vector register file is divided into multiple segments that can be selectively accessed based on the operation requirements. This segmentation allows the system to load only the necessary portion of data into the appropriate register segment, reducing the overall data volume that needs to be maintained in register files and thereby reducing power consumption while still providing the capability to handle large matrices when needed.
Data Source
AI summary
A processor includes a time counter, a vector coprocessor, and an extended vector register file for executing vector instructions and extending the data width of vector registers. The processor statically dispatches vector instructions with preset execution times based on a write time of a register in a coprocessor register scoreboard and a time counter provided to a vector execution pipeline.