Extended Via Inductor Structure for Higher On-Chip Q Factor

The patent extends the upper conductive vias vertically through multiple dielectric layers (first dielectric layer, second dielectric layer, and optionally third dielectric layer) to increase oxide thickness. This vertical extension into the third dimension increases the distance between the inductor and substrate, thereby reducing substrate loss and self-resonance effects while improving the Q factor of the on-chip inductor.

The patent divides the dielectric structure into multiple distinct layers (first dielectric layer with first oxide thickness, second dielectric layer with second oxide thickness, and optionally third dielectric layer with third oxide thickness). Each layer can be independently formed and controlled, allowing the total oxide thickness to be increased through stacking multiple thinner layers rather than requiring a single thick layer, thus improving Q factor while managing fabrication complexity.

The total oxide thickness is achieved by stacking multiple dielectric layers with individually controllable thicknesses. The first dielectric layer has a first oxide thickness, the second dielectric layer has a second oxide thickness, and the optional third dielectric layer has a third oxide thickness. This segmentation allows each layer to be formed with standard precision tolerances while achieving greater total thickness than a single layer would permit, thereby reducing substrate loss without excessively increasing manufacturing precision requirements.

The patent utilizes the vertical dimension by extending conductive vias through multiple stacked dielectric layers. This vertical stacking approach allows cumulative oxide thickness to increase (reducing substrate loss) while each individual layer thickness remains within manufacturable precision ranges. The multi-layer structure transforms a single-dimension thickness challenge into a multi-dimensional solution.