Extended Via Pixel Array Layout for Leakage-Limited Scaling
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Solution Overview
Problem
As pixel size shrinks, the size and spacing of conductive features in interconnect structures reach lower limits, leading to unmanageable leakage and capacitance effects, limiting further scaling down of digital image sensors.
Innovation Solution
The introduction of extended vias that span the combined height of a wire and a via, with a smaller footprint than the wire, replaces wires and adjoining vias at locations where sizing and spacing are at lower limits, relaxing constraints and allowing for further reduction in pixel size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pixel size is reduced to increase pixel density, then pixel density is improved, but conductive feature size and spacing reach lower limits causing unmanageable leakage and capacitance effects
Solution Approach 1:
The patent introduces extended vias that extend vertically into the substrate, utilizing the third dimension (depth) to reduce the horizontal footprint of conductive features. By extending vias downward into the substrate, the design achieves smaller surface area occupation while maintaining electrical connectivity, thereby enabling higher pixel density without compromising reliability through unmanageable leakage and capacitance effects.
Solution Approach 2:
The extended vias are nested within the substrate structure, with conductive material embedded deep within the substrate volume. This nesting approach allows the conductive features to occupy vertical space rather than horizontal space, effectively reducing the surface area required for each pixel while maintaining proper spacing and electrical performance.
2Length of moving object
If conductive feature size is reduced to enable further scaling, then pixel size is reduced, but leakage and capacitance effects become unmanageable
Solution Approach 1:
The patent transitions from two-dimensional surface-level conductive features to three-dimensional extended vias that penetrate into the substrate. This dimensional change allows conductive features to maintain adequate spacing and size for reliable electrical performance while occupying less surface area, enabling further pixel scaling without unmanageable leakage and capacitance effects.
Solution Approach 2:
The patent changes the geometric parameters of conductive features by extending vias vertically into the substrate rather than expanding them horizontally. This parameter change in the vertical dimension allows horizontal dimensions to be reduced, achieving smaller pixel sizes while maintaining reliability through proper control of leakage and capacitance effects.
3Quantity of substance
If wire and via spacing is reduced to increase pixel density, then pixel density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent resolves manufacturing precision challenges by moving the spacing dimension from the horizontal plane to the vertical dimension. Extended vias are spaced apart horizontally with relaxed requirements, while their vertical extension into the substrate provides the necessary electrical isolation and connectivity. This dimensional shift reduces the stringency of horizontal spacing precision requirements.
Solution Approach 2:
The extended via structure acts as an intermediary that decouples the spacing requirements between horizontal pixel density and vertical electrical performance. The via extends into the substrate to provide electrical connectivity while the horizontal spacing between vias can be larger, mediating between the requirements for high pixel density and relaxed manufacturing precision.
Data Source
AI summary
Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.