Extensible Network-on-Chip for Macro-Array Scaling
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Solution Overview
Problem
The existing processor arrays with a folded torus network-on-chip topology lack sufficient computing power for demanding applications, and increasing this power without modifying existing development tools is necessary.
Innovation Solution
An integrated circuit with compute nodes arranged in a torus topology and network extension units at each row or column end, allowing for external connection of input/output interfaces to form a macro-array with a single network, utilizing serial/parallel converters and a load balancer to manage data transmission and allocate bandwidth dynamically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the processor array size is increased to deliver more computing power, then the computing power is improved, but the device complexity increases
Solution Approach 1:
The patent divides the processor array into multiple independent integrated circuits, each containing a subset of compute nodes. These circuits are connected through extension units that interface with external serial channels. This segmentation allows the system to achieve higher computing power by combining multiple standard ICs while keeping each individual IC's complexity manageable and compatible with existing development tools.
Solution Approach 2:
The extension units serve multiple functions: they act as normal network nodes within the torus topology when operating in normal mode, and as interface units connecting to external serial channels when in extension mode. This multi-functionality enables the same hardware to operate in both standalone and interconnected configurations, simplifying the overall system architecture.
2Power
If network extension units are added to increase computing power, then the computing power is improved, but the network link complexity increases
Solution Approach 1:
The extension units operate in two dynamic modes: normal mode for internal network communication and extension mode for external connections. This dynamic operation allows the network links to be configured differently based on operational needs, maintaining simplicity for internal communications while enabling expansion for increased computing power.
Solution Approach 2:
The extension units act as intermediary components between the internal parallel bus network and external serial channels. They include parallel/series converters and series/parallel converters that mediate the interface between different communication protocols, simplifying the integration of external connections without complicating the internal network architecture.
3Speed
If parallel bus is used for internal communication, then the transmission rate is improved, but the bandwidth limitation increases
Solution Approach 1:
The patent segments the network links into multiple independent parallel buses within each integrated circuit, with extension units providing additional serial channels. This segmentation allows the system to achieve high transmission rates through parallel communication while managing bandwidth by distributing traffic across multiple links and using load balancing techniques.
Solution Approach 2:
The system changes the communication parameter from purely parallel to a combination of parallel and serial modes. Internal communication uses parallel buses for high-speed data transfer, while external connections use serial channels. The extension units dynamically switch between these modes, optimizing both transmission rate and bandwidth utilization.
4Ease of operation
If development tools are kept unchanged for compatibility, then the ease of operation is improved, but the adaptability to larger arrays decreases
Solution Approach 1:
By segmenting the large processor array into multiple standard-sized integrated circuits, the patent maintains compatibility with existing development tools designed for standard arrays. Each IC can be programmed using the same tools, while the collection of ICs forms a larger virtual array, thus maintaining ease of operation while achieving adaptability to larger configurations.
Solution Approach 2:
The extension units provide universal functionality that works whether or not external connections are used. This universality ensures that the same development tools and programming methods can be used for both standalone and interconnected configurations, maintaining ease of operation while enabling adaptability to various array sizes and topologies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables increased computing power by forming a macro-array with the same topology as individual arrays, allowing existing development tools to map tasks automatically, while maintaining high transmission rates and reducing complexity and bandwidth limitations.
Implementation Method 1
a parallel/series converter forming an outgoing serial channel for transmitting in series on a first external terminal of the circuit data presented in parallel on the segment
Implementation Method 2
a series/parallel converter forming an incoming serial channel for transmitting in parallel on the segment data arriving in series on a second external terminal of the integrated circuit
Data Source
AI summary
An integrated circuit comprises compute nodes arranged in an array; a torus topology network-on-chip interconnecting the compute nodes; and a network extension unit at each end of each row or column of the array, inserted in a network link between two compute nodes. The extension unit has a normal mode establishing the continuity of the network link between the two corresponding compute nodes, and an extension mode dividing the network link in two independent segments that are accessible from outside the integrated circuit.