3D Nonvolatile Memory Extension-Region Contacts for Smaller Chips
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing two-dimensional nonvolatile memory devices face challenges in increasing integration density and reducing production costs due to limitations in micro patterning technology, which are addressed by transitioning to three-dimensional memory cell arrangements.
Innovation Solution
The implementation of a nonvolatile memory device with a terraced stack structure and efficient use of space through the formation of input/output metal contacts and plate common source line contacts in extension regions, allowing for simultaneous manufacturing with channel structures, thereby reducing chip size and improving manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional planar nonvolatile memory device structure is used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional structure by forming terraced stacks with multiple levels. The memory cell strings are arranged in a three-dimensional configuration with first and second terraced stacks having different elevation levels, connected through shared bit lines and word lines. This dimensional transition enables significantly higher integration density while maintaining manufacturability through standardized three-dimensional fabrication processes.
2Quantity of substance
If three-dimensional memory cell arrangement is implemented, then integration density increases, but device complexity increases
Solution Approach 1:
The three-dimensional memory structure is segmented into distinct functional regions: first terraced stacks, second terraced stacks, shared bit lines, and word lines. Each segment performs a specific function and can be independently optimized. The first and second terraced stacks are separated in space but connected through shared conductors, allowing modular design and simplified fabrication while achieving high integration density.
Solution Approach 2:
The patent implements shared bit lines and word lines that serve multiple functions. The shared bit lines connect both first and second terraced stacks, and the word lines control memory cells across different levels. This multi-functionality reduces the total number of conductors needed, simplifying the device structure while maintaining high integration density.
3Ease of manufacture
If conventional contact structures are used, then manufacturing is easier, but chip size is larger
Solution Approach 1:
The contact structures are nested within the terraced stack architecture. Rear contact plugs are positioned at the bottom of the first terraced stack, extending through the substrate, while front contact plugs are integrated at the top of the second terraced stack. This nesting approach consolidates multiple contact functions into a compact three-dimensional arrangement, reducing chip size while maintaining ease of manufacture through vertical integration.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A nonvolatile memory device includes a plurality of metal lines extending in a first direction and stacked in a second direction crossing the first direction, a plurality of cell structures passing through the plurality of metal lines and extending in the second direction, a plurality of extension regions, a plate common source line contact connected with a common source line, extending in the first direction, and formed in least two of the plurality of extension regions that are not formed with the plurality of cell structures, and input/output metal contacts connected with an external connection pad, extending in the first direction, and formed with at least two of the plurality of extension regions that are not formed with the plate common source line contact.