3D Memory Word-Line Structure With Overlapping Pass Transistors
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity, particularly in transitioning from two-dimensional to three-dimensional memory cell arrangements.
Innovation Solution
A semiconductor device with a first structure comprising first and second memory regions and an extension region, featuring word lines and pass transistors with common and individual transistors, and a second structure with circuit regions overlapping the extension region, including common and individual gate electrodes, to enhance integration and reduce the overall plan area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple memory regions (first memory region, second memory region, and extension region) with distinct word line configurations. Each region can be independently controlled through common and individual word lines, allowing selective access to different memory segments. This segmentation enables the 3D structure to be managed as multiple manageable 2D-like layers, reducing operational complexity while maintaining high storage capacity.
Solution Approach 2:
The patent implements a hybrid architecture that combines 2D and 3D memory cell arrangements. The first and second memory regions use conventional 2D arrangements, while the extension region introduces a 3D configuration with intermediate word lines extending into the extension region. This dimensional transition allows increased storage capacity in the extension region without completely redesigning the entire memory structure, thereby managing complexity.
2Productivity
If circuit regions overlap memory regions in vertical direction to enhance integration, then integration efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The circuit region is positioned to overlap the extension region in the vertical direction, creating a nested configuration where circuit components are vertically integrated above memory structures. This nesting allows circuit elements (such as pass transistors and gate electrodes) to share the same planar footprint with memory cells, achieving high integration efficiency without requiring additional lateral space.
Solution Approach 2:
The patent utilizes vertical stacking to separate memory and circuit functions in the third dimension. Memory cells are arranged in the first and second regions at lower levels, while circuit regions are positioned above the extension region at higher levels. This vertical separation allows both memory and circuit components to coexist in the same planar area, improving integration efficiency while managing manufacturing precision through standardized vertical alignment processes.
3Adaptability or versatility
If common and individual word lines are used in extension region to improve memory access flexibility, then functionality is improved, but device complexity increases
Solution Approach 1:
The word line system is segmented into common word lines (first and second common word lines) that extend across the first memory region, extension region, and second memory region, and individual intermediate word lines (first and second intermediate individual word lines) that extend only into the extension region. This segmentation allows common word lines to provide global access across all regions while intermediate word lines provide selective access to the extension region, enhancing memory access flexibility without requiring completely independent control for each memory cell.
Solution Approach 2:
The common word lines serve multiple functions: they can address memory cells in the first memory region, second memory region, or both simultaneously, and they also provide addressing capability for the extension region when combined with individual intermediate word lines. This multi-functionality reduces the total number of word lines required compared to having completely independent word line sets for each region, thereby managing device complexity while improving access flexibility.
Data Source
AI summary
A semiconductor device includes a first structure having first and second memory regions, an extension region therebetween, and word lines; and a second structure having a circuit region overlapping the extension region. The word lines include first and second common word lines at different levels, and first and second intermediate individual word lines at a same level and spaced apart. Each of the first and second common word lines are in the first and second memory regions and the extension region. The first intermediate individual word line is in the first memory region and extends into the extension region at a level between the first and second common word lines. The second intermediate individual word line is in the second memory region and extends into the extension region. The circuit region includes pass transistors connected to the word lines. A pass transistor overlaps the word lines in the extension region.