External C-2C Capacitor Ladder for SRAM Compute-in-Memory
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Solution Overview
Problem
Conventional compute-in-memory (CiM) architectures face challenges with high circuit area overhead and reduced memory density due to the integration of capacitor ladder networks within static random-access memory (SRAM) arrays, and are limited by fixed weight data formats, which restrict flexibility and performance in neural network computations.
Innovation Solution
The solution involves an enhanced architecture where the capacitor ladder network is external to the SRAM array, using a reconfigurable out-of-SRAM C-2C-ladder-based multibit combination for analog MAC operations, allowing for increased memory density and flexibility in weight data formats by reducing circuit area overhead and enabling scalable and reconfigurable multibit computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the C-2C capacitor ladder network is integrated within the SRAM to perform MAC operations, then the neural network computation efficiency is improved, but the circuit area increases and memory density decreases
Solution Approach 1:
The patent extracts the C-2C capacitor ladder network from the SRAM array and places it externally. This separation allows the SRAM to maintain high memory density while the external capacitor network performs MAC operations, resolving the contradiction between computation efficiency and circuit area occupation.
Solution Approach 2:
The patent moves the capacitor ladder network from the two-dimensional SRAM plane to an external dimension, allowing independent optimization of memory density and computation efficiency without the area penalty of integration.
2Productivity
If the C-2C capacitor ladder network is integrated within the SRAM to perform MAC operations, then the neural network computation efficiency is improved, but the memory density decreases
Solution Approach 1:
By extracting the capacitor ladder network from the SRAM array, the patent preserves the SRAM's high memory density characteristics while enabling efficient analog MAC operations in the external network, thus resolving the contradiction between computation efficiency and memory density.
3Ease of manufacture
If conventional C-2C capacitor ladder network solutions are used with fixed data format, then the circuit implementation is simplified, but the flexibility and performance are reduced
Solution Approach 1:
The patent introduces reconfigurability to the external C-2C capacitor ladder network, allowing it to dynamically adapt to different weight data formats (e.g., INT8, INT4, binary). This dynamic configuration capability resolves the contradiction between implementation simplicity and format flexibility.
Solution Approach 2:
The external C-2C capacitor ladder network is designed to support multiple weight data formats through reconfiguration, making it a universal solution that can handle different neural network requirements while maintaining simplified circuit implementation for each specific format.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces capacitor circuit area overhead, increases memory and computation unit density, and provides reconfigurability in weight data formats, enhancing the efficiency and scalability of CiM arrays for neural network computations.
Implementation Method 1
a capacitor ladder network to conduct multiply-accumulate (MAC) operations on first analog signals and the multibit weight data
Data Source
AI summary
Systems, apparatuses and methods may provide for technology that includes a memory array to store multibit weight data and a capacitor ladder network to conduct multiply-accumulate (MAC) operations on first analog signals and multibit weight data, the capacitor ladder network further to output second analog signals based on the MAC operations, wherein the capacitor ladder network is external to the memory array. In one example, the capacitor ladder network includes a plurality of switches and the logic includes a controller to selectively activate the plurality of switches based on a data format of the multibit weight data.