External Capacitor Stacked on ROIC for Resolution
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Solution Overview
Problem
As photodetector technology advances, the need for increased resolution is hindered by reduced integration capacitance due to smaller pixel and capacitor sizes, which affects performance and fabrication costs.
Innovation Solution
Incorporating an external capacitor structure over a readout integrated circuit (ROIC) with additional capacitance, connected through connectors, to maintain or improve integration capacitance even with decreasing pixel pitch, allowing for further reductions in pixel size without compromising detector performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel size is reduced to increase the number of pixels and improve resolution, then resolution is improved, but integration capacitance decreases
Solution Approach 1:
The patent transitions from planar capacitors to three-dimensional stacked capacitor structures, utilizing the vertical dimension to increase capacitance. Multiple capacitor layers are stacked above each other, effectively using the third dimension (height) to provide additional capacitance without increasing the horizontal pixel area, thus resolving the contradiction between small pixel size and sufficient capacitance.
Solution Approach 2:
The patent implements nested capacitor structures where capacitors are stacked one above another in vertical layers. The first capacitor is formed in the substrate, and additional capacitors are stacked above it, creating a nested configuration where multiple capacitive elements occupy the same horizontal footprint but are arranged vertically, thereby increasing total capacitance within the constrained pixel area.
2Area of moving object
If capacitor size is reduced to maintain small pixel dimensions, then pixel size is reduced, but integration capacitance is compromised
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple capacitor layers above each other within the pixel structure. This allows the capacitor to achieve sufficient capacitance value without requiring large horizontal area, enabling small pixel dimensions while maintaining adequate integration capacitance through vertical stacking of capacitive elements.
Solution Approach 2:
The patent changes the structural parameters of the capacitor from a single planar layer to multiple stacked layers, increasing the effective capacitance area without increasing the pixel footprint. By modifying the capacitor architecture to include multiple vertical layers with conductive plates and dielectric materials, the capacitance is enhanced while keeping the horizontal pixel dimensions small.
3Measurement precision
If more pixels are incorporated to improve resolution, then resolution is improved, but detector size increases
Solution Approach 1:
The patent employs vertical stacking of capacitors in the third dimension, allowing each pixel to contain sufficient capacitance within a compact horizontal footprint. This enables the detector to accommodate more pixels in the same area, improving resolution without proportionally increasing the overall detector size, as each pixel maintains a small area through efficient vertical capacitor integration.
Data Source
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AI summary
Methods and structures of photodetectors are described. The structure may include a readout integrated circuit substrate having an internally integrated capacitor. The structure may additionally include an external capacitor overlying the readout integrated circuit substrate. The external capacitor may be coupled with the internally integrated capacitor of the readout integrated circuit substrate, and configured to operate in parallel with the internally integrated capacitor of the readout integrated circuit substrate. The structure may also include a detector overlying the external capacitor.