External DMA Peer-to-Peer Transfer in Reconfigurable Processors
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Solution Overview
Problem
Existing reconfigurable processor systems face significant communication overhead when implementing data-parallel training of neural networks, as they require external host processors to manage data sharing between reconfigurable processors, leading to inefficient performance and bandwidth issues.
Innovation Solution
A coarse-grained reconfigurable processor system with an external direct memory access (DMA) engine enables peer-to-peer communication between reconfigurable processors through Ethernet DMA transactions, allowing direct memory access without external host intervention, thereby reducing communication overhead and enhancing performance and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If external host processors are used to manage data sharing between reconfigurable processors, then system control and management are simplified, but communication overhead increases and performance decreases
Solution Approach 1:
The reconfigurable processors are equipped with external DMA engines that enable them to autonomously perform data transfers and gradient reductions without requiring external host processor intervention. Each reconfigurable processor can directly access memory and communicate with other reconfigurable processors through Ethernet DMA transactions, allowing the system to self-manage data sharing operations while maintaining simplified control architecture.
2Productivity
If peer-to-peer communication is implemented between reconfigurable processors, then communication overhead is reduced and bandwidth is enhanced, but device complexity increases
Solution Approach 1:
The reconfigurable processors incorporate universal external DMA engines that can perform multiple functions including direct memory access, inter-processor communication, and gradient reduction operations. This multi-functional approach enables peer-to-peer communication capabilities without requiring separate dedicated hardware for each communication function, thereby reducing the overall device complexity while maintaining high communication efficiency.
3Loss of time
If external DMA engines are integrated into reconfigurable processors, then direct memory access is enabled and communication overhead is reduced, but manufacturing complexity increases
Solution Approach 1:
The external DMA engine is merged with the reconfigurable processor core into a unified integrated unit. This combination allows the DMA functionality to be co-designed and co-manufactured with the reconfigurable logic, enabling direct memory access and peer-to-peer communication capabilities to be built into the processor fabric. The integration reduces data transfer time while managing manufacturing complexity through unified design and fabrication processes.
Data Source
AI summary
A coarse-grained reconfigurable processor (CGRP) system. The CGRP system includes a set of coarse-grained reconfigurable units (CGRUs) in a first coarse-grained reconfigurable processor that is coupled to a first memory, a network interface including an external direct memory access (DMA) engine coupled to the first memory, and a work queue associated with the external DMA engine.