External DRAM ECC Storage via Shared I/O Pins
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Solution Overview
Problem
Conventional systems for error detection and correction in external DRAM for GPUs incur significant cost burdens due to the need for additional I/O pins and DRAM chips to support ECC protection, which is not justified for applications that do not require high computational integrity.
Innovation Solution
A method that enables ECC protection of data in DRAM by storing both data and ECC data within the memory unit, using a read list structure to manage access requests and transmit data and ECC sectors efficiently, allowing the system to operate in both ECC and non-ECC modes without additional hardware costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC protection is implemented for external DRAM, then computational integrity is improved, but system cost and complexity increase due to additional I/O pins and DRAM chips
Solution Approach 1:
The patent merges the data storage and ECC protection functions into a single DRAM chip by storing both data bits and protection bits within the same memory device. This eliminates the need for separate DRAM chips dedicated to ECC storage, thereby reducing system cost and complexity while maintaining computational integrity through ECC protection.
Solution Approach 2:
The patent makes the existing DRAM chip multi-functional by enabling it to simultaneously store both user data and ECC protection bits. The DRAM chip thus serves dual purposes: primary data storage and error protection storage, eliminating the need for additional dedicated ECC storage hardware and reducing overall system complexity.
2Reliability
If additional DRAM chips are added for ECC storage, then error detection and correction capability is improved, but memory bandwidth and access efficiency deteriorate
Solution Approach 1:
By combining data and ECC bits into the same DRAM chip, the patent enables simultaneous access to both data and protection bits through a single memory interface. This eliminates the need for separate memory access channels that would be required if ECC data were stored on independent DRAM chips, thereby preserving memory bandwidth and access efficiency.
3Reliability
If I/O pins are added for ECC data transmission, then error protection is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges ECC protection functionality into the existing data I/O pathway by storing and transmitting ECC bits through the same I/O pins used for data transmission. This approach eliminates the need for additional dedicated I/O pins for ECC data, thereby reducing device complexity and manufacturing cost while maintaining robust error protection capabilities.
4Reliability
If ECC protection is implemented for all DRAM channels, then data integrity is improved, but system resource consumption and cost increase
Solution Approach 1:
The patent enables each DRAM channel to use its existing resources efficiently by making the DRAM chip multi-functional for both data and ECC storage. This eliminates the need for additional system resources such as separate DRAM chips and dedicated I/O pins for each channel, thereby providing comprehensive ECC protection across all channels without proportionally increasing system resource consumption.
Data Source
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AI summary
One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input/output (I/O) pins. Eliminating I/O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost.