FLASH Memory Interface With Dual Buses for Program Patching
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Solution Overview
Problem
Existing FLASH memory devices lack the ability to efficiently modify operation programs and facilitate seamless integration with both volatile and non-volatile memory components, leading to inefficiencies in data access and programming.
Innovation Solution
A FLASH memory device is designed with a separate FLASH memory interface outside the memory, featuring a first and second communication bus to connect non-volatile and volatile memory, along with coupling circuitry and a finite state machine to manage program patches and configuration values, enabling efficient data access and programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a FLASH memory device uses integrated internal interfaces for data access, then device complexity is reduced, but adaptability and ease of repair are limited
Solution Approach 1:
The FLASH memory device is segmented into separate functional modules: a FLASH memory core containing non-volatile memory cells, an external FLASH memory interface, and a volatile memory component. This segmentation allows each module to be independently designed, optimized, and replaced, thereby improving adaptability while managing device complexity through modular architecture.
Solution Approach 2:
An external FLASH memory interface acts as an intermediary between the FLASH memory core and external processing circuitry. This interface module provides standardized communication protocols and data bus connections, enabling flexible integration with various external systems while maintaining a clean separation of concerns that simplifies the overall device architecture.
2Productivity
If program modifications are performed in-place in FLASH memory, then productivity is improved, but reliability and manufacturing precision deteriorate
Solution Approach 1:
The system loads program patches into volatile memory before applying them to the FLASH memory. This preliminary action allows the FLASH memory to be programmed with updated instructions without disrupting the running system, improving productivity while maintaining reliability through safe, staged updates that can be verified before becoming active.
Solution Approach 2:
Program patches are created as copies of the original FLASH memory content with modifications applied to the volatile memory version. This copying approach allows parallel maintenance of the original reliable FLASH memory and the updated volatile version, enabling safe in-place updates that maintain both productivity and reliability through verified patch application.
3Ease of repair
If a separate FLASH memory interface is used with dual communication buses, then ease of repair and adaptability are improved, but device complexity increases
Solution Approach 1:
The interface is divided into separate communication buses: a first bus connecting the FLASH memory interface to non-volatile memory cells and a second bus connecting to volatile memory. This segmentation provides dedicated data pathways for different memory types, simplifying troubleshooting and repair by isolating communication paths while maintaining manageable complexity through standardized bus protocols.
Solution Approach 2:
The external FLASH memory interface serves multiple functions: it manages communication with both non-volatile and volatile memory, handles program patch application, stores configuration data, and provides access to control registers. This multi-functionality consolidates repair and maintenance operations into a single accessible interface, improving ease of repair while the modular design keeps complexity manageable.
Data Source
AI summary
A FLASH memory device includes a FLASH memory having an array of non-volatile memory cells and a volatile memory. A FLASH memory interface is arranged outside of the FLASH memory, and a first communication bus couples the FLASH memory interface to the array of memory cells. A second communication bus couples the FLASH memory interface to the volatile memory.