External Flash Translation Layer Controller for Multi-SSD Systems

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Solution Overview

Problem

Current SSDs face inefficiencies due to device-based FTL being isolated from hosts, leading to reduced system performance and resource overconsumption, while host-based FTLs consume significant host resources.

Innovation Solution

A control unit with a flash translation layer module handles address mapping and background processing for multiple SSDs, reducing host resource consumption by performing computational processing and managing I/O operations, and eliminating the need for extensive microprocessors and DRAM in each SSD.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If device-based FTL is used with more microprocessors and DRAM in each SSD, then the SSD controller computation power is improved, but the host resources are not utilized and system performance degrades due to isolation

Engineering Contradiction:
ImproveSSD controller computation powerVSAvoidsystem performance
Core Design Contradiction:
PowerVSProductivity

Solution Approach 1:

The patent merges the FTL functionality from individual SSD controllers into a shared external controller that serves multiple SSDs. This consolidation allows the FTL to be executed once for multiple drives rather than duplicating computation power across each SSD, improving overall system productivity while maintaining the computational capabilities needed for address mapping and data management.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces an external controller as an intermediary between the host and multiple SSDs. This mediator handles the FTL operations and address mapping, allowing the host to communicate with SSDs without direct involvement in FTL computations. The intermediary enables resource sharing and coordination among multiple SSDs, resolving the isolation problem while maintaining computational efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of information

If host-based FTL is used, then the host gains visibility into LBA-to-PBA mapping, but host CPU and DRAM resources are significantly consumed

Engineering Contradiction:
Improvehost visibility into mappingVSAvoidhost CPU and DRAM consumption
Core Design Contradiction:
Loss of informationVSUse of energy by moving object

Solution Approach 1:

The external controller acts as an intermediary that maintains the LBA-to-PBA mapping information, providing the host with visibility into mapping relationships without requiring the host to perform FTL computations. The intermediary handles the computational burden of maintaining and updating mapping tables, thereby reducing host CPU and DRAM consumption while preserving host visibility into address mappings.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If device-based FTL is used in each SSD, then each SSD operates independently, but system efficiency decreases due to lack of communication between drives

Engineering Contradiction:
ImproveSSD independenceVSAvoidsystem efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent combines multiple independent SSDs under a single external controller that manages FTL operations for all drives. This merging enables communication and coordination between SSDs through the shared controller, allowing for system-level optimizations such as load balancing, wear leveling across drives, and efficient garbage collection, thereby improving overall system efficiency while maintaining individual SSD functionality.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11132291B2System and method of FPGA-executed flash translation layer in multiple solid state drives
Publication Date: 2021.09.28 CLOUD INTELLIGENCE ASSETS HOLDING (SINGAPORE) PTE LTD
  • US11132291B2 patent drawing
  • US11132291B2 patent drawing
  • US11132291B2 patent drawing

AI summary

One embodiment facilitates data storage. During operation, the system receives data to be stored in a non-volatile memory of a storage device. The system determines, by a flash translation layer module of a control unit which is distinct from the storage device, a physical page address at which the data is to be stored in the non-volatile memory, wherein the flash translation layer module of the control unit determines physical page addresses for data to be stored in a plurality of storage devices. The system stores, by the flash translation layer module of the control unit, a mapping between a logical page address for the data and the physical page address. The system writes the data to the non-volatile memory at the physical page address.