External Hardware Clock Rate Calculation

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Solution Overview

Problem

Existing methods for calculating a processor's clock rate are inefficient and inaccurate due to the need for software intervention and configuration, which consumes processor cycles and introduces interrupt interference, leading to unreliable and coarse-grained timing intervals.

Innovation Solution

An apparatus and method that utilize a hardware element external to the processor to capture performance data at fine intervals, calculating the clock rate based on differences in performance metrics without software intervention, allowing continuous monitoring and accurate clock rate determination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If software intervention is used to calculate clock rate, then the calculation can be performed, but processor cycles are consumed and interrupt interference is introduced

Engineering Contradiction:
Improveclock rate calculation accuracyVSAvoidprocessor cycle efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent extracts the clock rate calculation function from the processor's software execution environment and implements it in a separate performance monitoring unit. This allows the calculation to be performed using dedicated hardware resources, eliminating the consumption of processor cycles and interrupt interference while maintaining measurement accuracy through specialized hardware counters and timing mechanisms.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a performance monitoring unit as an intermediary between the processor and the clock rate calculation process. This intermediate hardware component captures performance data directly from processor signals without requiring software intervention, thereby preventing both processor cycle consumption and interrupt interference while still enabling accurate clock rate determination.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If software-based performance data capture is used, then performance metrics can be obtained, but timing intervals become coarse-grained and less accurate

Engineering Contradiction:
Improvetiming interval accuracyVSAvoidmeasurement response time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent replaces the software-based timing mechanism with a hardware-based performance monitoring unit that uses dedicated counters and timers. This hardware substitution enables fine-grained timing intervals by directly capturing processor clock signals and performance events at hardware level, eliminating the coarse-grained timing limitations inherent in software polling and interrupt-driven approaches.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If hardware element external to processor is used, then non-intrusive monitoring is achieved, but device complexity increases

Engineering Contradiction:
Improvemonitoring accuracyVSAvoidsystem architecture complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the performance monitoring unit with the processor package, placing the external hardware monitoring element in close physical and functional integration with the processor. This combination allows non-intrusive monitoring through direct access to processor signals while minimizing system architecture complexity by consolidating components rather than adding separate external monitoring systems.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9952956B2Calculating the clock frequency of a processor
Publication Date: 2018.04.24 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9952956B2 patent drawing
  • US9952956B2 patent drawing
  • US9952956B2 patent drawing

AI summary

Apparatuses, methods, systems, and computer program products are disclosed for calculating a clock rate of a processor. A baseline data module receives a first set of performance data associated with a processor. The performance data is generated using a hardware element that captures performance data for the processor. The hardware element is external to the processor. An update data module receives a second set of performance data associated with the processor a predefined time interval after the first set of performance data is received. The second set of performance data corresponds to the first set of performance data. A rate module calculates a clock rate for the processor based on the first set of performance data and the second set of performance data.