External Memory Connection Unit for Mobile Device Scalability
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Solution Overview
Problem
Mobile devices face performance degradation due to insufficient main memory capacity when handling multiple tasks simultaneously, especially with limited memory size, leading to issues with multi-tasking capabilities.
Innovation Solution
A device architecture that incorporates an external memory connection unit to increase main memory capacity by sharing the command-address bus and using dedicated and variable data lines, with a flag signal to manage operation modes and maintain point-to-point connections between the memory controller and internal and external memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the main memory capacity is increased by adopting an external memory, then the multi-tasking performance is improved, but the device complexity increases
Solution Approach 1:
The memory system is segmented into internal memory and external memory components. The external memory connection unit is separated as a distinct module that can be independently connected to the memory controller, allowing the memory capacity to be extended without redesigning the entire memory subsystem.
Solution Approach 2:
The memory controller is designed with universal interfaces that can communicate with both internal memory and external memory through the memory bus. The external memory connection unit uses the same command-address bus and data bus infrastructure, enabling a single controller to manage multiple memory types without requiring separate dedicated controllers.
2Quantity of substance
If the external memory is connected to extend memory capacity, then the main memory capacity is increased, but the data communication efficiency may be affected
Solution Approach 1:
The external memory connection unit merges with the existing memory bus infrastructure by sharing the command-address bus and data bus. This integration allows the external memory to communicate with the memory controller through the same pathways used for internal memory, eliminating the need for separate communication channels and maintaining data communication efficiency.
Solution Approach 2:
The external memory connection unit acts as an intermediary between the external memory and the memory controller. It includes signal lines that interface the external memory with the memory bus, and a flag signal generation mechanism that mediates the connection state to the memory controller, ensuring proper protocol adherence and data communication efficiency.
3Device complexity
If the command-address bus is shared by internal and external memory, then the device complexity is reduced, but the signal integrity may be compromised
Solution Approach 1:
The memory controller dynamically configures the command-address bus based on the connection state. When external memory is connected, the controller adjusts the driving strength of the bus drivers and manages the flag signal to indicate the extended memory mode, ensuring proper signal integrity for shared bus operation.
Solution Approach 2:
The memory controller changes operational parameters such as driver strength and bus timing when external memory is detected through the flag signal. By adjusting these parameters based on the memory configuration state, the system maintains signal integrity while sharing the command-address bus between internal and external memory.
4Adaptability or versatility
If the data bus width is divided for internal and external memory, then the scalability is improved, but the communication speed may be reduced
Solution Approach 1:
The data bus is segmented into dedicated data lines for internal memory and variable data lines that can be dynamically assigned. In base mode, the full data bus width is available to internal memory. In memory extension mode, the data bus is divided to allocate appropriate bandwidth to external memory while maintaining connectivity.
Solution Approach 2:
The data bus configuration is dynamic and changes based on the memory mode. The memory controller switches between base mode and memory extension mode depending on the flag signal, thereby dynamically adjusting which data lines are active and their assignment to internal or external memory, optimizing performance for the current configuration.
Data Source
AI summary
A device includes a memory controller, a memory bus coupled to the memory controller, an internal memory and an external memory connection unit. The internal memory may be directly connected to the memory controller through the memory bus. The external memory connection unit may connect an external memory directly to the memory controller through a portion of signal lines in the memory bus, and may generate a flag signal indicating whether the external memory is connected to the external memory connection unit.