External Memory Controller for Scalable Data Center Nodes
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Solution Overview
Problem
Current CPU packages face limitations in memory capacity to core ratios and I/O per core, leading to inefficient resource utilization when scaling for large-scale data processing, as they cannot accommodate the expanded requirements of modern applications, resulting in wasted resources and non-optimal configurations.
Innovation Solution
Implementing an external master memory controller that is communicably coupled to processors but separate from the CPU package, allowing for independent scaling of memory and storage capacities, and using a system fabric for communication between nodes to access remote memory and I/O resources, thereby breaking the dependency on CPU vendor-defined ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If memory controllers are integrated into CPU packages, then system integration and communication efficiency are improved, but memory capacity to core ratios and I/O per core are limited
Solution Approach 1:
The patent separates the memory controller from the CPU package into an independent external memory controller. This segmentation allows the memory controller to be independently scaled and configured without being constrained by CPU package limitations, thereby resolving the contradiction between system integration and memory capacity to core ratios.
Solution Approach 2:
The memory controller is extracted from the CPU package and placed as an external component. This extraction removes the constraint of fixed memory capacity to core ratios that exists when the controller is integrated, allowing flexible configuration of memory resources independent of the CPU package.
2Quantity of substance
If CPU packages are scaled to meet largest resource requests, then system capacity is improved, but excess resources in other categories are wasted
Solution Approach 1:
The patent enables dynamic scaling of memory and I/O resources independently of CPU cores through the external memory controller architecture. This allows the system to be configured with optimal ratios for specific workloads rather than scaling to satisfy the largest single request, thereby reducing resource waste while maintaining adequate capacity.
Solution Approach 2:
The external memory controller allows independent adjustment of memory capacity and I/O parameters without changing the CPU package configuration. This parameter independence enables optimization of resource allocation for specific application requirements, preventing the waste that occurs when scaling to meet peak demands across all resource types.
3Quantity of substance
If multiple CPU packages are used to increase memory and I/O capacity, then resource capacity is improved, but core utilization efficiency deteriorates
Solution Approach 1:
By segmenting the memory controller from the CPU package, the patent allows memory and I/O resources to be independently scaled without requiring additional CPU packages. This enables increasing memory and I/O capacity while maintaining the same number of cores, thereby preserving core utilization efficiency.
4Ease of manufacture
If CPU packages include fixed ratios of memory and I/O, then manufacturing simplicity is improved, but adaptability to different applications deteriorates
Solution Approach 1:
The memory controller is extracted from the CPU package, removing the fixed ratio constraint. This allows different configurations of memory and I/O resources to be provided with the same CPU package by simply configuring the external memory controller, thereby improving adaptability to different applications without complicating CPU manufacturing.
Data Source
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AI summary
A computing system is disclosed herein. The computing system includes a computing node and a remote memory node coupled to the computing node via a system fabric. The computing node includes a plurality of processors and a master memory controller. The master memory controller is external to the plurality of processors. The master memory controller routes requests corresponding to requests from the plurality of processors across the system fabric to the remote memory node and returns a response.