External Nonvolatile Memory Interface with Digital PLL Clock Alignment
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Solution Overview
Problem
Current System on Chip (SoC) devices face challenges with slow access times and high power consumption due to the limitations of existing nonvolatile memory technologies, particularly with external nonvolatile memories using Serial Peripheral Interface (SPI), which are not low power and have high latency, and the dilemma of using older or newer technologies that restrict transistor count and upgradeability.
Innovation Solution
A high-speed, low-power interface between a processing device and external nonvolatile memory using CMOS signaling with a reduced frequency clock and digital PLL for clock phase alignment, allowing for serial data transmission up to 2.5 Gbits/sec and enabling efficient power management by disabling the clock during data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If external nonvolatile memory uses SPI interface, then device complexity is reduced, but access speed becomes slow and power consumption increases
Solution Approach 1:
The patent changes the interface parameters from traditional SPI to a custom high-speed interface operating at 2.5 Gbits/sec, fundamentally altering the data transmission rate parameter to achieve both fast access and low power consumption while maintaining reasonable device complexity
Solution Approach 2:
The patent implements dynamic clock gating that enables the clock signal to be disabled during periods when data is not being transmitted, allowing the interface to adapt its power consumption and operational state dynamically based on data transfer requirements
2Ease of manufacture
If external nonvolatile memory uses SPI interface, then ease of manufacture is improved, but power consumption becomes high
Solution Approach 1:
The patent employs periodic clock gating where the clock signal is periodically enabled and disabled based on data transfer activity, creating a rhythmic on/off pattern that significantly reduces average power consumption while maintaining ease of manufacture through standard CMOS signaling
Solution Approach 2:
The patent changes the operational parameters by implementing reduced frequency clocking during idle periods and full frequency during active transfer, dynamically adjusting the clock frequency parameter to optimize power consumption without compromising manufacturing simplicity
3Use of energy by moving object
If clock frequency is reduced for power saving, then power consumption is reduced, but data transmission speed decreases
Solution Approach 1:
The patent implements dynamic frequency scaling where the clock frequency automatically adjusts between reduced and full speed based on data transfer requirements, creating a dynamic system that optimizes the power-speed tradeoff in real-time
Solution Approach 2:
The patent uses a digital PLL that retains its state and can quickly reacquire synchronization when the clock is reenabled, performing preliminary preparation work during idle periods so that full-speed transmission can resume immediately without significant delay
4Adaptability or versatility
If digital PLL retains state for clock reacquisition, then adaptability to clock disabling is improved, but device complexity increases
Solution Approach 1:
The patent uses a digital PLL that creates and maintains a digital copy of the clock state and phase information, allowing the system to retain essential timing information in digital form during clock disabling periods without requiring complex analog circuitry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The interface achieves high-speed data transfer with low latency and reduced power consumption, allowing for efficient communication between processing units and external nonvolatile memory, optimizing transistor count and power usage while supporting upgradeability.
Implementation Method 1
a clock phase alignment block, which utilizes a digital PLL to align a phase of the memory serdes clock with the incoming data signal
Implementation Method 2
the second device comprises a multiplier in communication with the reduced frequency clock to create a memory serdes clock having a frequency equal to the frequency of the serdes clock
Data Source
AI summary
An interface between two devices is disclosed. To consume power, the signals used in the interface utilize CMOS signalling. Further, to achieve high speed, a reduced frequency clock is transmitted from one device to the second device. The second device has a clock multiplier to recreate the original clock. Both devices utilize a clock phase alignment block which aligns the phase of the clock with the incoming data. The clock phase alignment block utilizes a digital PLL to consume power. Further, since the digital PLL retains its state, the reduced frequency clock may be disabled when data is not being transmitted. This interface may be used to transmit serial data at rates up to and exceeding 2.5 Gbits/sec.