Automated External Memory Module Selection in High-Level Synthesis
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Solution Overview
Problem
Current high-level synthesis tools require manual selection and modification of behavioral descriptions to allocate specific memory modules to external memory, making the circuit design process inefficient.
Innovation Solution
A circuit design support apparatus that includes a binding data acquiring unit and a memory module selecting unit to automatically select an external memory module based on constraint conditions, eliminating the need for manual selection and optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If high-level synthesis tools automatically allocate array variables to memory modules, then the design process becomes more automated, but the designer loses control over which specific memory modules are used, requiring manual intervention to implement external memory architecture
Solution Approach 1:
The high-level synthesis tool automatically performs memory module allocation and external memory identification without requiring designer intervention. The tool analyzes the behavioral description, generates binding data with memory module information, and autonomously determines which memory modules should be implemented as external memory based on the allocation results, thereby making the system self-sufficient in this design task.
Solution Approach 2:
The invention separates the memory allocation process into distinct components: binding data generation, memory module selection, and external memory identification. This segmentation allows the tool to systematically process different aspects of memory management independently, improving both automation capability and design control simultaneously.
2Manufacturing precision
If the designer manually modifies behavioral description to allocate specific memory modules to external memory, then precise control over memory allocation is achieved, but the design time and complexity increase significantly
Solution Approach 1:
The high-level synthesis tool performs memory module allocation as a preliminary step before finalizing the design. By generating binding data that includes memory module allocation information in advance, the tool prepares the necessary allocation decisions upfront, eliminating the need for time-consuming manual modifications later in the design process while maintaining precise control over which memory modules are allocated to external memory.
3Reliability
If array variables are allocated to large memory modules in high-level synthesis, then the behavioral description is faithfully implemented, but the LSI area increases due to large internal memory allocation
Solution Approach 1:
The invention introduces binding data as an intermediary between the behavioral description and the memory module allocation. The binding data contains memory module information that serves as a mediator to guide the allocation process, enabling the tool to determine which memory modules should be implemented externally rather than internally, thus reducing LSI area while maintaining faithful implementation of the behavioral description.
Data Source
AI summary
A binding data acquiring unit acquires binding data describing a plurality of memory modules as functional modules of a design target circuit. A memory module selecting unit selects an external memory module to be implemented as an external memory outside of the design target circuit from the memory modules described in the binding data on the basis of a constraint condition on the design target circuit.