External Memory Translation Lookaside Buffer for Address Translation
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Solution Overview
Problem
Modern microprocessors face high virtual-to-physical address translation overhead due to large memory spaces and low reference locality, leading to increased TLB miss rates and page table walk latency, which is not effectively addressed by increasing TLB size or changing page sizes without compromising compatibility and efficiency.
Innovation Solution
An external memory translation lookaside buffer (EMTLB) is introduced to cache virtual-to-physical address translations evicted from the on-chip TLB, reducing the number of page table walks by providing a larger cache for translations that are not frequently accessed, thus improving address translation efficiency without altering the page table structure or impacting existing memory allocation algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the TLB size is increased to reduce translation latency, then address translation speed improves, but device complexity and cost increase
Solution Approach 1:
The translation cache is segmented into two distinct parts: an on-chip TLB for frequently accessed translations and an off-chip EMTLB in external memory for less frequently accessed translations. This segmentation allows the system to maintain a small, fast on-chip TLB while extending caching capacity to external memory, avoiding the complexity of a large monolithic TLB.
Solution Approach 2:
The invention extends the translation cache from the traditional on-chip dimension to the external memory dimension. By placing the EMTLB in external memory rather than integrating it fully on-chip, the system gains larger cache capacity without proportionally increasing on-chip area and complexity.
2Measurement precision
If a page table walk is performed to resolve physical memory address, then translation accuracy is ensured, but translation time increases significantly
Solution Approach 1:
The system performs preliminary caching of address translations in both the on-chip TLB and off-chip EMTLB before they are needed for actual memory access. By pre-caching translations that are evicted from the TLB in external memory, the system prepares translation results in advance, so when a page table walk would otherwise be required, the translation can be quickly retrieved from the EMTLB instead.
3Productivity
If the TLB cache is enlarged to reduce miss rates, then address translation efficiency improves, but on-chip area and cost increase
Solution Approach 1:
The invention extracts the less frequently accessed translation cache from the on-chip TLB and places it in external memory as the EMTLB. This extraction allows the on-chip TLB to remain small and area-efficient while still providing large overall cache capacity through the external memory component, thus improving translation efficiency without increasing on-chip area.
4Productivity
If page size is changed to improve translation performance, then translation efficiency may improve, but compatibility with existing systems is compromised
Solution Approach 1:
The EMTLB is designed to work universally with existing page table structures and memory allocation algorithms without requiring changes to the page size or page table format. The system can handle both large and small pages, and the EMTLB adapts to different page sizes and memory allocation strategies, maintaining compatibility while improving translation performance.
Data Source
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AI summary
Methods, devices, and systems for virtual address translation. A memory management unit (MMU) receives a request to translate a virtual memory address to a physical memory address and searching a translation lookaside buffer (TLB) for a translation to the physical memory address based on the virtual memory address. If the translation is not found in the TLB, the MMU searches an external memory translation lookaside buffer (EMTLB) for the physical memory address and performs a page table walk, using a page table walker (PTW), to retrieve the translation. If the translation is found in the EMTLB, the MMU aborts the page table walk and returns the physical memory address. If the translation is not found in the TLB and not found in the EMTLB, the MMU returns the physical memory address based on the page table walk.