External NAND Control for Runtime Memory Algorithm Evaluation
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Solution Overview
Problem
Existing storage devices face challenges in predicting memory cell characteristics during development, leading to increased development time and costs due to the need for remaking chips to test new algorithms, and limited algorithm evaluation options.
Innovation Solution
Incorporation of an external NAND control (ENC) circuit with a deserializer, buffer memory, and data loader to receive and generate control signals based on data from an external device, allowing for the testing of various algorithms without chip remaking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple operation algorithms are individually implemented and selectively tested to determine which algorithm will be used, then the optimal algorithm can be selected, but significant production time and costs are needed for manufacturing chips
Solution Approach 1:
The patent implements a dynamic algorithm selection mechanism where the controller can switch between multiple operation algorithms based on real-time memory cell characteristics. The system includes a deserializer that receives algorithm data from an external device and a data loader that generates control signals based on this data, enabling flexible algorithm changes without physical chip remaking. This dynamic approach allows the system to adapt to different memory cell characteristics while avoiding the time-consuming process of manufacturing multiple chip variants.
Solution Approach 2:
The patent changes the parameter of algorithm selection from a fixed manufacturing-stage decision to a runtime-configurable parameter. By receiving algorithm data from an external device through the deserializer and processing it through the data loader, the system can modify operational parameters dynamically. This allows different algorithms to be tested and selected based on actual memory cell characteristics without requiring physical chip modifications or remaking.
2Adaptability or versatility
If multiple operation algorithms are individually implemented and selectively tested to determine which algorithm will be used, then the optimal algorithm can be selected, but significant costs are needed for manufacturing chips
Solution Approach 1:
The patent creates a virtual copy of the algorithm selection process that eliminates the need for physical chip manufacturing for each algorithm variant. Instead of manufacturing multiple chips with different algorithms embedded, the system uses an external device to provide algorithm data that is deserialized and processed to generate control signals. This virtual copying approach allows multiple algorithms to be tested and evaluated without the significant manufacturing costs associated with producing multiple chip variants.
Solution Approach 2:
The patent introduces an intermediary system consisting of the deserializer and data loader that mediates between the external algorithm data source and the memory device operation. This intermediary layer allows algorithm selection to be decoupled from the physical chip manufacturing process. The deserializer receives algorithm data from an external device and the data loader generates appropriate control signals, serving as a mediator that enables flexible algorithm selection without requiring costly chip remaking for each algorithm variant.
3Adaptability or versatility
If algorithms are tested by remaking chips, then new algorithms can be evaluated, but development time increases
Solution Approach 1:
The patent implements preliminary action by receiving and processing algorithm data from an external device before actual memory cell testing. The deserializer deserializes the algorithm data and the data loader generates control signals in advance, allowing algorithms to be prepared and evaluated without waiting for chip remaking. This preliminary processing of algorithm data enables rapid evaluation of multiple algorithms using the same physical chip, significantly reducing development time compared to traditional chip remaking approaches.
4Adaptability or versatility
If the number of control algorithms and control signals increases to match increased storage capacity, then more memory cell characteristics can be verified, but the complexity of the system increases
Solution Approach 1:
The patent extracts the algorithm data from the internal control logic and places it in an external device. The deserializer and data loader handle the interface between the external algorithm source and the internal memory control circuitry. This extraction separates the complexity of algorithm storage and variation from the physical chip design, allowing numerous control algorithms and control signals to be supported without increasing the internal complexity of the memory device itself. The external device bears the complexity burden while the memory device maintains a simpler, more manageable control structure.
Data Source
AI summary
A storage device may include an external NAND control (ENC) circuit and a nonvolatile memory device. The ENC circuit may include a deserializer configured to deserialize data received from an external device, a buffer memory configured to store the data, and a data loader configured to generate a control signal based on the data. The nonvolatile memory device may include a memory cell array, a voltage generator, a row decoder, and a page buffer. The data may include control information associated with implementing a hardware algorithm.