External NAND Controller With ECC for Newer Flash Reliability
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Solution Overview
Problem
Existing NAND flash memory controllers are unable to support newer NAND devices with lower reliability and increased error rates, as they require stronger error correction capabilities than the built-in controllers in host processors, limiting the ability to benefit from the cost advantages of these devices.
Innovation Solution
A NAND controller that interfaces between a host device and a NAND flash memory device, featuring electronic circuitry on a separate die with both host-type and flash-type NAND interfaces, and an error correction module to correct errors, allowing it to communicate with both the host and the NAND device using a NAND interface protocol, thereby supporting devices with varying reliability levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If host processors with built-in NAND controllers are used, then device complexity is reduced and ease of operation is improved, but reliability deteriorates because they cannot provide sufficient error correction for newer low-reliability NAND devices
Solution Approach 1:
The patent introduces an external NAND controller as an intermediary device between the host processor and the NAND flash memory. This external controller possesses advanced error correction capabilities that the built-in host controller lacks, thereby resolving the contradiction by mediating between the host's simplicity needs and the memory's reliability requirements.
2Ease of manufacture
If newer NAND flash memory devices with lower reliability are used, then cost is reduced, but reliability deteriorates due to increased error rates requiring stronger error correction
Solution Approach 1:
The external NAND controller serves as a mediator that enables the system to use cheaper, lower-reliability NAND devices while compensating for their deficiencies through advanced error correction mechanisms, thus resolving the cost-reliability tradeoff.
Solution Approach 2:
The external controller changes the error correction parameter capability, providing stronger ECC (Error Correction Code) functionality that allows the system to tolerate the higher error rates of newer NAND devices, thereby enabling use of lower-cost memory.
3Reliability
If a standalone NAND controller with advanced error correction is introduced, then reliability is improved by correcting errors from lower-reliability devices, but device complexity increases
Solution Approach 1:
The patent segments the error correction functionality into a separate external controller device, allowing the host processor to remain simple while the specialized controller handles the complex error correction tasks. This segmentation resolves the contradiction by isolating complexity to where it is most effective.
4Device complexity
If built-in NAND controllers are used, then device complexity is minimized, but adaptability deteriorates because they cannot support successive generations of NAND devices with varying reliability characteristics
Solution Approach 1:
The external NAND controller is designed with universal error correction capabilities that can adapt to support multiple generations of NAND devices with varying reliability characteristics. This multi-functionality resolves the contradiction by providing both simplicity to the host and adaptability to different memory technologies.
Data Source
AI summary
A NAND controller for interfacing between a host device and a flash memory device (e.g., a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g. a host-type interface, for example, a NAND interface) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e.g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed. Methods for assembling the aforementioned systems, and for reading and writing data using NAND controllers are also disclosed.