External Nonvolatile Memory Clock Multiplication and Encryption
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Solution Overview
Problem
Current System on Chip (SoC) devices face challenges with slow access times and high power consumption due to limitations in nonvolatile memory (NVM) technology, which also lack security features for field upgradability and compatibility with current fabrication technology.
Innovation Solution
An external nonvolatile memory device with a CMOS interface that uses a clock signal multiplication for high-speed data transmission, incorporates an encryption/decryption block for secure data transfer, and supports secure boot, allowing for field upgradability and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If external nonvolatile memory uses SPI interface, then field upgradability is achieved, but access time increases and speed decreases
Solution Approach 1:
The patent replaces the traditional SPI mechanical interface with a CMOS serial interface that uses clock signal multiplication. The clock input signal is multiplied by an integer factor (e.g., 2x, 4x, 8x) to generate higher frequency internal clocks, enabling data transfer rates significantly faster than standard SPI while maintaining the external memory architecture for field upgradability.
Solution Approach 2:
The patent changes the operational parameters of the memory interface by using variable clock multiplication factors. The clock multiplier can dynamically adjust the frequency ratio between the input clock and internal operation clocks, allowing the system to optimize between speed and power consumption based on operational requirements, achieving both fast access and energy efficiency.
2Adaptability or versatility
If external nonvolatile memory uses SPI interface, then field upgradability is achieved, but power consumption increases
Solution Approach 1:
The patent implements periodic clock signaling where the clock input is held in a deasserted (low-power) state when no data transmission is occurring. The clock signal is activated only during data transfer periods, creating a periodic on/off pattern that dramatically reduces average power consumption compared to continuously active SPI interfaces, while still enabling field upgradability through the external memory connection.
Solution Approach 2:
The patent changes the power state parameters dynamically by deasserting the clock signal during idle periods and asserting it only during active data transmission. This parameter change from continuous to intermittent operation reduces average power consumption while maintaining the capability for field upgradable code through the external nonvolatile memory interface.
3Adaptability or versatility
If external nonvolatile memory is used, then field upgradability and technology compatibility are achieved, but security is lost
Solution Approach 1:
The patent introduces an encryption/decryption block as an intermediary between the external nonvolatile memory and the processing unit. This security intermediary encrypts data before it is written to the external memory and decrypts it during read operations, protecting against code injection and monitoring attacks while maintaining field upgradability. The intermediary adds security functionality without preventing external memory access for code updates.
Data Source
AI summary
An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.