External NVM Emulates On-Chip ISP for FPGA Firmware Updates

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Field programmable gate arrays (FPGAs) lack on-chip embedded non-volatile memory (NVM), making it difficult to provide in-system programming (ISP) for firmware updates, and existing workarounds are limited by firmware size and require manual intervention, which is not suitable for field upgradability.

Innovation Solution

The system emulates on-chip ISP features using external non-volatile memory (NVM) configured to communicate with an FPGA-based ISP manager via interfaces like USB, UART, Ethernet, enabling secure, reliable, and persistent firmware updates by detecting an ISP mode and updating FPGA CPU control registers with system parameters and firmware images.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If FPGAs use on-chip embedded NVM for ISP, then firmware update reliability is improved, but device complexity and cost increase

Engineering Contradiction:
Improvefirmware update reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an external NVM device as an intermediary component to store firmware images and system parameters. This external NVM acts as a mediator between the host processor and the FPGA, enabling ISP functionality without modifying the FPGA's internal structure. The external NVM contains an ISP manager that handles firmware updates, system parameter storage, and coordination with the host, thus achieving reliable firmware updates without increasing FPGA device complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If FPGAs use external NVM for ISP, then adaptability to different FPGA devices is improved, but firmware update speed decreases

Engineering Contradiction:
Improveadaptability to different FPGA devicesVSAvoidfirmware update speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent implements preliminary action by pre-storing multiple firmware images and system parameters in the external NVM before they are needed. The ISP manager in the external NVM prepares the firmware update data in advance, validates it, and loads it into appropriate buffers or memory regions before the actual update process begins. This preliminary preparation reduces the time required during the actual firmware update operation, mitigating the speed penalty of using external NVM while maintaining broad adaptability across different FPGA devices.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If manual intervention is required for firmware updates, then security is improved, but ease of operation deteriorates

Engineering Contradiction:
ImprovesecurityVSAvoidease of operation
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent implements self-service through the ISP manager in the external NVM, which autonomously handles firmware update operations. The ISP manager receives firmware images from the host processor, validates their integrity using cryptographic checksums, automatically loads them into the appropriate memory regions, and coordinates the update process without requiring manual intervention. This self-service capability maintains security through automated validation while significantly improving ease of operation, as the entire update process is initiated and managed through standard communication interfaces without human involvement.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12061701B2On-chip NVM ISP emulation in FPGA
Publication Date: 2024.08.13 SEAGATE TECH LLC
  • US12061701B2 patent drawing
  • US12061701B2 patent drawing
  • US12061701B2 patent drawing

AI summary

An implementation of a device disclosed herein includes a field programmable gate array (FPGA) circuit and a non-volatile memory (NVM) configured external to the FPGA circuit and configured to communicate with an in-system programming (ISP) manager configured on the FPGA circuit, wherein the NVM is further configured to store one or more system parameters and one or more firmware images, wherein the ISP manager being configured to detect an ISP mode in response to receiving a signal from an ISP switch and executing an ISP state machine to update one or more FPGA CPU control registers with one or more of the system parameters and the one or more of the firmware images stored on the NVM.