External PLL FPGA Clock Alignment for Low-Latency Phase Matching
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) face a technical challenge in synchronizing receiver side and transmitter side clock signals, leading to unwanted latency and processing delays, which are undesirable in high-frequency applications like high-frequency trading where accuracy to the microsecond is crucial.
Innovation Solution
A field programmable gate array system with an external phase controller that provides phase matching between the receiver and transmitter clocks, using a deserializer and serializer to generate aligned clock signals and a phase control circuit to adjust the transmitter side clock signal based on phase differences, eliminating the need for clock domain crossing circuits that introduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock domain crossing circuit is included in the FPGA to synchronize receiver and transmitter clock signals, then phase synchronization is achieved, but processing delay increases
Solution Approach 1:
The patent extracts the phase synchronization function from the FPGA internal clock domain crossing circuit and relocates it to an external phase controller device. This separation allows the FPGA to process data without internal phase synchronization delays, while the external device handles clock alignment independently, thus resolving the contradiction between achieving phase synchronization and minimizing processing delay.
Solution Approach 2:
The patent introduces an external phase controller as an intermediary device between the receiver and transmitter clock sources. This mediator performs phase synchronization externally, allowing the FPGA to operate with minimal internal delay while still achieving the required clock alignment through the intermediary's phase adjustment capabilities.
2Reliability
If phase synchronization is implemented within the FPGA, then clock alignment is achieved, but processing throughput decreases
Solution Approach 1:
The patent extracts the phase synchronization functionality from the FPGA's internal processing path and places it in an external phase controller. This extraction removes the bottleneck from the critical data processing path, allowing the FPGA to maintain high throughput while the external device handles clock alignment separately, thus resolving the contradiction between clock alignment and processing throughput.
3Reliability
If internal clock domain crossing circuits are used, then phase matching is achieved, but latency increases
Solution Approach 1:
The patent introduces an external phase controller as an intermediary that performs phase matching independently of the FPGA's internal data path. This intermediary handles clock domain alignment externally, allowing the FPGA to process data with minimal latency while the intermediary ensures proper phase matching through dedicated phase adjustment circuits outside the critical processing path.
Data Source
AI summary
The present invention relates to a field programmable gate array system that provides phase control with minimal latency.