External PLL Clock Alignment for Low-Latency FPGA Processing
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) face a technical challenge in synchronizing receiver and transmitter clock signals, which introduces unwanted latency and delays in processing, particularly in high-frequency applications like high-frequency trading where precise timestamp accuracy is crucial.
Innovation Solution
A field programmable gate array system with an external phase controller that aligns the receiver and transmitter clock signals by using a phase detector and controller to adjust the transmitter side clock signal, eliminating the need for clock domain crossing circuits and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock domain crossing circuit is used to synchronize receiver and transmitter clocks, then phase synchronization is achieved, but processing latency increases
Solution Approach 1:
The patent extracts the clock domain crossing functionality from the FPGA fabric and implements it using external phase-locked loops outside the FPGA. This removes the need for internal clock domain crossing circuits that would add latency to the processing path, while still achieving the required phase synchronization between receiver and transmitter clocks.
Solution Approach 2:
The patent introduces external phase-locked loops as intermediary devices between the receiver and transmitter clock domains. These PLLs act as mediators that synchronize the clock phases without requiring data to pass through latency-inducing clock domain crossing circuits within the FPGA fabric.
2Reliability
If phase synchronization is implemented within FPGA, then clock alignment is achieved, but processing throughput decreases
Solution Approach 1:
The patent extracts the phase synchronization function from the FPGA processing fabric and implements it externally using dedicated phase-locked loop circuits. This allows the FPGA to operate at full throughput without dedicating processing resources to clock synchronization, thereby maintaining high productivity while achieving reliable clock alignment.
3Reliability
If clock synchronization circuitry is added to FPGA, then phase matching is improved, but device complexity increases
Solution Approach 1:
The patent extracts the complex phase matching functionality from the FPGA device and implements it in external dedicated hardware. This reduces the FPGA's internal circuit complexity by removing the need for integrated clock domain crossing and phase synchronization logic, while still achieving the required phase matching performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables sub-microsecond processing throughput without introducing unnecessary delay, achieving phase synchronization between receiver and transmitter clocks, thereby enhancing processing efficiency and reducing latency in high-frequency applications.
Implementation Method 1
a phase detector operationally connected to the first clock output pin and the second clock output pin of the second interface of the field programmable gate array, and wherein the phase detector is configured to compare the third phase of the receiver side clock signal to the fifth phase of the transmitter side clock signal and to generate a phase difference indicator signal based on a difference between the third phase of the receiver side clock signal and the fifth phase of the transmitter side clock signal
Implementation Method 2
an adjustable oscillator operationally connected to the phase controller and configured to receive the adjustment information as well as operationally connected to the second reference clock pin of the first interface of the field programmable gate array, wherein the adjustable oscillator is configured to generate the second clock signal including the second frequency and the second phase based on the adjustment information
Data Source
AI summary
The present invention relates to a field programmable gate array system that provides phase control with minimal latency.