External PLL FPGA Clock Alignment Without Domain Crossing
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) face a technical challenge in synchronizing receiver side and transmitter side clock signals, which introduces unwanted latency and delays in processing, particularly in high-frequency applications like high-frequency trading where precise timestamp accuracy is crucial.
Innovation Solution
A field programmable gate array system with an external phase controller that provides phase matching between receiver and transmitter clocks, using a deserializer and serializer to convert serial data streams into parallel data streams and generate clock signals, and an adjustable oscillator to align phases without clock domain crossing, thereby eliminating unnecessary latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock domain crossing circuit is used to synchronize receiver and transmitter clocks, then phase synchronization is achieved, but processing delay increases
Solution Approach 1:
The patent extracts the clock domain crossing function from the FPGA fabric and implements it externally using a separate phase-locked loop circuit. This removes the need for internal clock domain crossing circuits that introduce delay, while still achieving phase synchronization between receiver and transmitter clocks through the external PLL's phase detector and feedback mechanism.
Solution Approach 2:
The patent introduces an external phase-locked loop as an intermediary device between the receiver and transmitter clock domains. The PLL acts as a mediator that generates a synthesized clock signal phase-aligned to the reference clock, enabling synchronization without direct clock domain crossing within the FPGA fabric, thus avoiding the associated delays.
2Reliability
If internal phase-locked loop is used for clock synchronization, then clock alignment is achieved, but processing throughput decreases
Solution Approach 1:
The patent extracts the phase-locked loop functionality from the FPGA's internal logic fabric and implements it as an external dedicated circuit. This separation allows the FPGA to focus on high-speed data processing while the external PLL handles clock synchronization, thereby maintaining both clock alignment and high processing throughput without the performance penalty of integrating PLL logic within the fabric.
3Reliability
If clock domain crossing is implemented within FPGA fabric, then phase matching is achieved, but latency increases
Solution Approach 1:
The patent introduces an external phase-locked loop as an intermediary device that generates a synthesized clock signal phase-aligned to the reference clock. This external mediator enables phase matching between receiver and transmitter domains without requiring data to traverse delay-intensive clock domain crossing circuits within the FPGA fabric, thus reducing latency while maintaining phase coherence.
Data Source
AI summary
The present invention relates to a field programmable gate array system that provides phase control with minimal latency.