External SCRC Switches for Semiconductor Voltage Stability
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing sub-threshold current, which leads to increased power consumption and chip size due to local voltage drops and time lags caused by irregular logic circuit operations, affecting data reliability and memory access speed.
Innovation Solution
The implementation of a sub-threshold current reduction circuit (SCRC) with strategically placed switches that couple power supply voltages to logic circuits, using a mesh-structured circuit design with SCRC voltage lines and switches to minimize voltage drops and propagate power supply noise, thereby reducing sub-threshold current and improving chip efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SCRC switches are located near logic circuits to provide SCRC voltage, then local voltage drops are prevented, but chip area increases and manufacturing complexity increases
Solution Approach 1:
The patent moves SCRC switches from the chip interior to the exterior, utilizing the dimensional space outside the chip boundary. This allows the switches to remain close to logic circuits for voltage stability while not consuming additional chip area, as they are positioned in the external wiring structure rather than on the chip substrate.
Solution Approach 2:
The patent introduces a pad as an intermediary element that mediates between the external SCRC switches and the internal logic circuits. The pad serves as a connection point that allows voltage regulation to occur externally while maintaining electrical connection to internal circuits, thus preventing voltage drops without requiring physical proximity of switches to logic circuits on the chip.
2Reliability
If SCRC switches are located near logic circuits to provide SCRC voltage, then local voltage drops are prevented, but device complexity increases
Solution Approach 1:
The patent extracts the SCRC switches from the internal circuit structure and relocates them to the external wiring. This separation simplifies the internal chip design by removing complex voltage regulation components from the chip interior, while still providing voltage stabilization functionality through externally positioned switches connected via pads.
3Productivity
If power supply voltage is provided from uppermost-level conductive layer through pad to M3 pad, then power distribution is achieved, but voltage drops and time lags occur affecting data reliability
Solution Approach 1:
The patent implements preliminary voltage regulation by positioning SCRC switches externally before voltage is distributed to logic circuits. The switches pre-regulate voltage on power supply lines before the voltage reaches internal circuits, preventing voltage drops and time lags from occurring during normal operation, thus maintaining data reliability while achieving effective power distribution.
Data Source
AI summary
Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a pad included in a pad formation area that receives a power voltage; a sub-threshold current reduction circuit (SCRC) included in a peripheral circuit area including a via disposed on a first side of the peripheral circuit area, and a wiring that couples the pad to the via. The SCRC further includes: a voltage line coupled to the via; a logic gate circuit that propagates a signal; an SCRC voltage line coupled to the logic gate circuit; and a SCRC switch disposed in proximity to the via and couples the SCRC voltage line to the voltage line.