External State Cache for Processor Failover

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Solution Overview

Problem

High-availability computing systems face inefficiencies due to the need for redundant components to maintain state consistency and performance when one processor fails, leading to performance penalties and increased power consumption.

Innovation Solution

Implementing an external state cache that allows processors to share and preserve their state, enabling seamless resumption of processing without requiring a second processor to recreate the state, using dedicated state-dump ports to minimize performance impact and independent power supplies to ensure reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If identical components are operated in parallel to preserve data and enable quick switching upon failure, then reliability is improved, but performance deteriorates due to the penalty of two components doing the work of one

Engineering Contradiction:
Improvesystem availabilityVSAvoidprocessing performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent creates a copy of the processor state (registers, cache contents, program counter) and stores it in an external state cache. This allows a backup processor to resume execution without requiring a second active processor, thus maintaining reliability while avoiding the performance penalty of parallel operation. The state copy enables the backup to take over seamlessly without both processors needing to do simultaneous work.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The system performs preliminary action by continuously maintaining a current state copy in the external state cache before failure occurs. This pre-prepared state information allows the backup processor to immediately resume execution after a failure, eliminating the need for both processors to operate in parallel and reducing the performance overhead while ensuring quick failover.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If a second processor is used to take over upon failure, then reliability is improved, but device complexity and power consumption increase

Engineering Contradiction:
Improvesystem availabilityVSAvoidprocessor redundancy configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the state information from the processor and stores it in a separate external state cache. This separation allows a single processor to operate with a backup capability, rather than requiring two full processors. The state cache takes out only the necessary state data, reducing the complexity and power consumption associated with maintaining a second full processor while still providing failover capability.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If state is preserved in external cache, then productivity is improved by avoiding restart, but device complexity increases due to additional cache infrastructure

Engineering Contradiction:
Improveprocess resumption speedVSAvoidexternal state cache system
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The external state cache serves multiple functions: it acts as a state storage mechanism for failover, provides a backup copy for potential recovery, and enables quick resumption of processing. This multi-functionality justifies the additional infrastructure by providing both reliability improvement and productivity enhancement through avoided restarts, making the added complexity worthwhile.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8812781B2External state cache for computer processor
Publication Date: 2014.08.19 HEWLETT PACKARD ENTERPRISE DEV LP
  • US8812781B2 patent drawing
  • US8812781B2 patent drawing
  • US8812781B2 patent drawing

AI summary

A processor can write its state to an external state cache. Thus, in the event of a processor failure, the stored state can be read and assumed, either by the original processor or another processor. Thus, a process can be resumed from the stored state rather than reconstructed from initial conditions.