External Timestamp Registers for Multi-Core Trace Correlation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Debugging software programs in systems with multiple processor cores is challenging due to the difficulty in correlating the code executed between processor cores, particularly when one core stalls waiting for another to complete a task, making it hard to determine the activity causing the stall.
Innovation Solution
A method and system that insert marker values into trace data from each processor core to enable correlation of contemporaneously executed instructions, using timestamp registers and log buffers to identify stall conditions and correlate data across processor cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processor cores are used to work together, then system productivity and operational capability are improved, but the difficulty of detecting and measuring the execution state and correlating trace data between cores increases
Solution Approach 1:
The patent introduces timestamp registers as intermediary components that mediate between multiple processor cores and the trace data collection system. Each processor core has its own timestamp register that automatically records execution timestamps, serving as a mediator that facilitates the correlation of trace data from different cores without requiring complex inter-core communication or manual synchronization mechanisms.
Solution Approach 2:
The patent implements preliminary action by automatically recording timestamps in timestamp registers before trace data is generated or lost. The timestamp registers continuously update with execution timestamps, ensuring that when trace data is collected later, the correlation information is already captured and stored, eliminating the need for real-time correlation during data collection.
2Reliability
If one processor core stalls waiting for another processor core, then task interdependence and system coordination are improved, but the ability to identify the cause of the stall through trace data analysis deteriorates
Solution Approach 1:
The timestamp registers serve as intermediaries that capture and preserve the temporal relationship between processor cores during stall conditions. When one core stalls waiting for another, the timestamp registers continuously record the execution state of both cores, maintaining the correlation information that would otherwise be lost during the stall period, enabling later analysis of the stall cause.
Solution Approach 2:
The patent implements feedback by continuously monitoring and recording the execution state of processor cores through timestamp registers. This creates a feedback mechanism where the system automatically tracks and stores information about inter-core dependencies and stall conditions, providing the data necessary to analyze and identify the root causes of stalls without interrupting normal operation.
3Ease of operation
If trace data from multiple processor cores is collected separately, then data collection simplicity is improved, but the ability to correlate contemporaneously executed instructions deteriorates
Solution Approach 1:
The patent applies local quality by providing each processor core with its own dedicated timestamp register that is locally updated with execution timestamps. This local timestamping mechanism ensures that each core's trace data is independently collected with precise timing information, while the uniform timestamp format across all cores enables accurate correlation without requiring complex centralized coordination.
Data Source
AI summary
A method and system of inserting marker values used to correlate trace data as between processor cores. At least some of the illustrative embodiments are integrated circuit devices comprising a first processor core, a first data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the first processor core, a second processor core communicatively coupled to the first processor core, and a second data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the second processor core. The integrated circuit device is configured to insert marker values into the data of the first and second processor cores which allow correlation of the data such that contemporaneously executed instruction are identifiable.