External Virtualization Logic for Processor Transaction Interception

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Solution Overview

Problem

Conventional software-based virtualization incurs a performance penalty, and hardware-supported virtualization requires costly chip design and power-consuming circuitry, limiting it to single-level CPU virtualization and increasing development time.

Innovation Solution

Implementing external virtualization hardware that intercepts transactions between processors and virtual devices, allowing processors without internal virtualization support to interact with virtual I/O devices without performance penalties, using external address trapping logic to selectively route transactions and provide signals for secure mode transitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If software-based virtualization is used, then virtual devices can be implemented, but performance penalty occurs

Engineering Contradiction:

Improvevirtual device implementationVSAvoidperformance

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent introduces an intermediary device (virtualization device) positioned between the processor and virtual devices to handle virtualization operations. This intermediary captures processor transactions, determines whether they are directed to virtual devices, and routes them appropriately, thereby eliminating the performance penalty of software-based virtualization while maintaining hardware compatibility.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces software-based virtualization mechanisms with hardware-based interception and routing logic. By substituting software processing with hardware-level transaction interception and routing, the system achieves virtual device support without the performance overhead associated with software interpretation and processing.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If hardware-supported virtualization is implemented, then performance penalty is reduced, but chip cost and development time increase

Engineering Contradiction:

ImproveperformanceVSAvoidchip cost and development time

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

The patent extracts the virtualization support functionality from the processor chip itself and places it in a separate, externally connected virtualization device. This extraction allows standard processors without built-in virtualization support to achieve hardware-level virtualization performance while avoiding the increased chip manufacturing costs and development time associated with integrating virtualization features directly into the processor.

Inventive Principle:

Principle #2Taking out (Extraction)

3Productivity

If hardware-supported virtualization is implemented, then circuitry remains power-consuming even when not employed

Engineering Contradiction:

ImproveperformanceVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic activation of virtualization functionality through event-driven interception logic. The virtualization device selectively activates processing only when processor transactions are actually directed to virtual devices, rather than maintaining continuously active virtualization circuitry. This dynamic approach reduces power consumption while preserving hardware-level performance when virtualization is needed.

Inventive Principle:

Principle #15Dynamics

4Productivity

If hardware-supported virtualization is implemented, then complete CPU virtualization is required, limiting to single level

Engineering Contradiction:

ImproveperformanceVSAvoidvirtualization level flexibility

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal virtualization interface that can accommodate multiple levels of virtualization (CPU, device, function) without requiring complete CPU virtualization. The interception device provides multi-functional support that works with various processor architectures and virtualization requirements, enabling flexible multi-level virtualization implementations beyond the constraints of traditional hardware-supported approaches.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS7600082B2Virtualization logic

Publication Date: 2009.10.06 HEWLETT PACKARD ENTERPRISE DEV LP

AI summary

Systems, methodologies, media, and other embodiments associated with externally trapping transactions are described. One exemplary system embodiment includes an external virtualization logic configured to be operably connected to a processor that does not include internal virtualization support. The example system may include a data store for storing a trappable memory address and a transaction that causes the external virtualization logic to produce a trap.