External Way Allocation Circuitry for Shared Cache Partitioning
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Solution Overview
Problem
Modern processors lacking hardware support for way allocation in shared cache systems experience increased cache thrashing, as they cannot effectively allocate cache ways for different processes, leading to inefficient memory management.
Innovation Solution
Implementing external way allocation circuitry that intercepts memory requests, reads partition identifiers from storage, and attaches them to requests before sending them to a cache control unit, which determines designated ways in the shared cache based on these identifiers, allowing for equitable cache allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If way allocation hardware is integrated into processor cores, then cache allocation precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts the way allocation functionality from the processor core and places it in an external circuit. The external way allocation circuit maintains partition identifier tables and handles cache way assignment, while the processor core itself remains unchanged. This extraction resolves the contradiction by achieving precise cache allocation without increasing processor core complexity.
Solution Approach 2:
The patent introduces an external way allocation circuit as an intermediary between the processor core and the shared cache. This intermediary component handles the complex partition identifier table management and way allocation logic, allowing the processor core to remain simple while still achieving precise cache allocation through the intermediary's coordination.
2Device complexity
If way allocation is implemented in software, then device complexity is reduced, but processing speed decreases
Solution Approach 1:
The external way allocation circuit serves as a hardware intermediary that bridges software configuration and hardware execution. Software populates the partition identifier table in the external circuit, but the actual way allocation decisions are made in hardware, achieving both low complexity and high speed.
Solution Approach 2:
The partition identifier table is populated in advance by software during system initialization or configuration phases. This preliminary action allows the hardware external circuit to make rapid way allocation decisions without real-time software intervention, thus achieving high processing speed while maintaining software controllability.
3Productivity
If multiple processes share the same cache ways, then cache utilization is improved, but cache thrashing increases
Solution Approach 1:
The patent segments the shared cache into distinct partitions assigned to different processes through way allocation. Each process receives dedicated cache ways based on its needs, preventing cache thrashing caused by multiple processes competing for the same cache lines while maintaining high overall cache utilization through efficient partition management.
Solution Approach 2:
The patent applies local quality by assigning different cache ways to different processes based on their specific requirements. The partition identifier table enables each process to access specific cache partitions optimized for its workload characteristics, reducing thrashing while maintaining high utilization through localized cache allocation.
Data Source
AI summary
An apparatus includes a plurality of processor cores; a shared cache connected to the plurality of processor cores; a cache control unit connected to the shared cache; and a way allocation circuitry connected to at least one of the plurality of processor cores. The way allocation circuitry is external to the plurality of processor cores. The cache control unit and the way allocation circuitry are cooperatively configured to process an intercepted memory request with respect to designated ways in the shared cache, the designated ways being based on a partition identifier and a partition table.