Extra Gate Nanosheet Integration via Segmented Doping and Patterning
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Solution Overview
Problem
The integration of high voltage extra gate (EG) devices with standard nanosheet devices is challenging due to the requirement for thicker gate dielectrics in EG devices, which conflicts with the optimal spacing and dimensions necessary for capacitance benefits in nanoscale CMOS devices.
Innovation Solution
A method is developed to integrate EG and single gate (SG) devices by forming highly doped regions, patterning nanosheet structures, and creating a dummy gate structure, allowing for the formation of thicker gate dielectrics in EG devices while maintaining the necessary spacing and dimensions for both EG and SG devices on the same chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thicker gate dielectric is used for high voltage EG devices, then voltage operation capability is improved, but device spacing and capacitance benefits deteriorate
Solution Approach 1:
The patent divides the device structure into separate EG device regions and SG device regions, allowing each to be optimized independently. EG devices receive thicker gate dielectric for high voltage operation, while SG devices maintain thinner gate dielectric for optimal capacitance and spacing, resolving the contradiction between voltage capability and capacitance benefits
Solution Approach 2:
Different gate dielectric thicknesses are applied to different device regions based on their specific requirements. The EG device region receives thicker gate dielectric locally, while the SG device region maintains thinner gate dielectric, enabling each region to optimize its performance characteristics without compromising the other
2Productivity
If tighter device spacing is used for nanoscale CMOS, then capacitance benefits are improved, but device size scaling deteriorates
Solution Approach 1:
The patent segments the chip into distinct EG and SG device regions, allowing SG devices to achieve tight spacing for capacitance benefits while EG devices are positioned separately with adequate spacing for their thicker gate dielectric requirements, thus maintaining both capacitance benefits and proper device dimensions
3Ease of manufacture
If standard nanosheet structure is used, then manufacturing simplicity is improved, but integration of high voltage and low voltage devices deteriorates
Solution Approach 1:
The patent divides the nanosheet structure into separate EG device regions and SG device regions within the same stack, allowing standard nanosheet manufacturing processes to be used while enabling co-integration of both high voltage and low voltage devices on the same chip
Solution Approach 2:
The nanosheet stack structure serves multiple functions simultaneously - it provides the substrate for both EG devices with thicker gate dielectric and SG devices with thinner gate dielectric, enabling a single manufacturing process to produce devices with different voltage characteristics from the same structural platform
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the co-integration of high voltage EG devices with low voltage SG devices, achieving thicker gate dielectrics for EG devices while maintaining optimal spacing, thus overcoming the limitations of device size scaling and capacitance benefits.
Implementation Method 1
doping a surface of a substrate in exposed areas where extra gate (EG) devices are to be formed to form a highly doped region
Implementation Method 2
A gate structure is formed in and over the dummy gate trench wherein the at least one bottommost sheet forms a device channel for the EG device
Data Source
AI summary
A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is patterned to form nanosheet structures. A dummy gate structure is formed over and between the nanosheet structures. An interlevel dielectric layer is formed. The dummy gate structures are removed. SG regions are blocked, and top sheets are removed from the nanosheet structures along the dummy gate trench. A bottommost sheet is released and forms a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the bottommost sheet. A gate structure is formed in and over the dummy gate trench wherein the bottommost sheet forms a device channel for the EG device.