Extra Inner Spacers in Gate-All-Around Devices for Gate Capacitance
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Solution Overview
Problem
Conventional horizontal gate-all-around (GAA) devices suffer from excessive parasitic capacitance between the gate and source/drain, which degrades device performance, particularly in high-frequency applications.
Innovation Solution
The fabrication process involves forming a stack of semiconductor layers with different material compositions, where a low-k dielectric spacer layer is deposited around high-k dielectric spacer layers to increase the thickness of the dielectric material, reducing parasitic capacitance by creating a 'bridge' that separates the metal gate structure from the source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional HGAA device structure is used, then gate control is improved and short-channel effects are reduced, but parasitic capacitance between gate and source/drain becomes excessive
Solution Approach 1:
The patent introduces a dielectric layer as an intermediary substance between the metal gate structure and source/drain regions. This dielectric layer acts as a mediator that reduces the direct capacitive coupling while maintaining the gate's control function over the channel, thereby resolving the contradiction between gate control and parasitic capacitance.
Solution Approach 2:
The patent adds a vertical dimension to the gate structure by extending the dielectric layer in the vertical direction between the gate and source/drain. This dimensional extension increases the separation distance without compromising the horizontal gate control, effectively reducing parasitic capacitance while preserving device performance.
2Reliability
If dielectric layer thickness is increased to reduce parasitic capacitance, then device performance is improved, but device area increases
Solution Approach 1:
The patent applies dielectric material selectively in specific local regions where parasitic capacitance occurs (between gate and source/drain), rather than uniformly throughout the entire device. This localized application reduces capacitance where needed while minimizing the overall area increase, as the dielectric is confined to critical interfaces rather than expanding the entire device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance, improving device performance and reliability, especially in high-frequency operations by increasing the dielectric thickness and using low-k dielectric materials to minimize capacitance.
Implementation Method 1
conventional HGAA devices may have an excessive parasitic capacitance between the gate and the source/drain, which could adversely degrade device performance
Implementation Method 2
a low-k dielectric spacer layer is deposited around high-k dielectric spacer layers to increase the thickness of the dielectric material
Data Source
AI summary
A semiconductor device includes a plurality of nanostructures. The nanostructures each contain a semiconductive material. A plurality of first spacers circumferentially wrap around the nanostructures. A plurality of second spacers circumferentially wrap around the first spacers. A plurality of third spacers is disposed between the second spacers vertically. A gate structure surrounds the second spacers and the third spacers.