EXTRA NoC Router Pipeline Stage Segmentation for Clock Frequency
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Solution Overview
Problem
The clock frequency of SMART routers is limited by the critical pipeline stage that combines SSR traversal and SA-G, which severely restricts the performance of Network-on-Chip (NoC) systems due to the time required for these processes.
Innovation Solution
The EXTRA NoC separates the SA-G pipeline stage into two distinct pipeline stages, allowing for a higher clock frequency and reducing latency by enabling serial execution of SR and SA-G processes, and inserting registers between pipeline stages to regulate timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the SA-G pipeline stage combines SSR traversal and switch allocation-global processes, then the router structure remains simple, but the clock frequency is limited due to the critical pipeline stage duration
Solution Approach 1:
The patent segments the combined SA-G pipeline stage into separate pipeline stages: SSR generation and transmission is separated from SA-G arbitration. This segmentation reduces the critical path duration by allowing parallel execution of SSR traversal and local switch allocation, thereby increasing the clock frequency while managing complexity through structured separation of functions
2Loss of time
If the router uses a single-cycle multi-hop traversal approach, then latency is reduced, but the pipeline stage time required for SSR and SA-G processes increases
Solution Approach 1:
The patent implements preliminary action by generating SSR signals in advance during the SA-L pipeline stage, before the SA-G arbitration phase. This allows downstream routers to prepare their arbitration decisions ahead of time, reducing the actual traversal time and overall latency while maintaining manageable pipeline stage durations through overlapping execution
Data Source
AI summary
This invention is related to an Express Traversal (EXTRA) Network on Chip (NoC) comprising a number of EXTRA routers. The EXTRA NoC comprises a Buffer Write and Route Computation (BW/RC) pipeline, a Switch Allocation-Local (SA-L) pipeline, a Setup Request (SR) pipeline, a Switch Allocation-Global (SA-G) pipeline, and a Switch Traversal and Link Traversal (ST/LT) pipeline. The BW/RC pipeline is configured to write an incoming flit to an input buffer(s) of a start EXTRA router and compute the route for the incoming head flit by selecting an output port to depart from the start EXTRA router. The SA-L pipeline is configured to arbitrate the start EXTRA router to choose an input port and an output port for a winning flit. The SR pipeline is configured to handle the transmission of a number of SR signals from the start EXTRA router to downstream EXTRA routers.