Multi-Level Interconnects for Extreme Temperature IC Chips
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor integrated circuits using wide band gap materials, such as silicon carbide, face challenges in maintaining reliable operation for extended periods at high temperatures above 500 C, with previous implementations limited to fewer than 10 interconnected transistors functioning for more than 200 hours.
Innovation Solution
A multi-level interconnect process is developed, involving the deposition of semiconductor devices on a substrate with insulating layers, patterned photoresist, and etching to create vias and metal interconnects, using durable materials like TaSi2 and Hafnium for ohmic contacts, and oxidation-resistant protective layers, allowing for prolonged operation at extreme temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional IC materials and processing are used, then manufacturing ease and cost are improved, but reliability at temperatures above 125 C deteriorates
Solution Approach 1:
The patent changes the material parameters by substituting conventional interconnect materials (Al, Cu) with high-temperature stable materials (TaSi2, W, Mo, Pt, Pd, Ir, Rh, Ru). This material parameter change enables the interconnect structure to maintain reliability at temperatures above 125 C while preserving the standard CMOS fabrication process compatibility
Solution Approach 2:
The patent employs composite material structures including: (1) TaSi2 as a diffusion barrier and conductive material, (2) combinations of multiple metals (W, Mo, Pt, Pd, Ir, Rh, Ru) with different properties to achieve both conductivity and high-temperature stability, and (3) integrated structures combining these materials with standard CMOS devices. These composite materials provide both ease of manufacture through standard processes and reliability at elevated temperatures
2Temperature
If wide band gap semiconductor transistors are used, then operating temperature capability is improved, but device complexity and interconnection reliability deteriorate
Solution Approach 1:
The patent applies local quality by implementing high-temperature stable materials (TaSi2, W, Mo, Pt, Pd, Ir, Rh, Ru) specifically in the interconnect regions where thermal stress and oxidation are most severe, while maintaining standard CMOS device structures. This localized application of specialized materials solves the interconnection reliability problem without requiring complex modifications to the entire device architecture
Solution Approach 2:
The patent uses thin film deposits (50-200 nm thickness) of high-temperature materials that can be deposited using standard sputtering equipment. These thin films provide the necessary high-temperature protection and conductivity without adding significant complexity, effectively acting as disposable protective and conductive layers that can be integrated into standard fabrication flows
3Ease of manufacture
If standard metal interconnects are used, then manufacturing simplicity is improved, but durability at 500 C for prolonged periods deteriorates
Solution Approach 1:
The patent changes the material parameters by substituting conventional interconnect materials (Al, Cu) with high-temperature stable materials (TaSi2, W, Mo, Pt, Pd, Ir, Rh, Ru). This material parameter change enables the interconnect structure to maintain reliability at temperatures above 125 C while preserving the standard CMOS fabrication process compatibility
Solution Approach 2:
The patent ensures continuous useful action by designing interconnect structures that maintain electrical conductivity and structural integrity continuously at 500 C for prolonged periods (thousands of hours). The use of oxidation-resistant materials and diffusion barriers ensures that the interconnect function continues without degradation, unlike conventional materials that would oxidize and fail
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process enables integrated circuits with over 10 transistors to function reliably for more than 1000 hours at temperatures greater than 500 C, demonstrating improved durability and complexity in high-temperature applications.
Implementation Method 1
deposited by sputtering
Implementation Method 2
The deposited layers are then annealed
Data Source
AI summary
A process of fabrication and the resulting integrated circuit device is made of patterned metal electrical interconnections between semiconductor devices residing on and forming extremely harsh environment integrated circuit chips. The process enables more complicated wide band gap semiconductor integrated circuits with more than one level of interconnect to function for prolonged time periods (over 1000 hours) at much higher temperatures (500 C).