Wrap-Around Extrinsic Base HBT Layout for Lower Rb and Higher fMAX

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current integration schemes for heterojunction bipolar transistors (HBTs) result in high collector-base capacitance (Ccb) and high base resistance (Rb), which limit device scaling and performance in terms of cut-off frequencies (fT/fMAX) and breakdown voltage (BVceo).

Innovation Solution

A heterojunction bipolar transistor with a wrap-around extrinsic base and silicide on the extrinsic base is fabricated, where the extrinsic base surrounds the intrinsic base and emitter, allowing for a larger surface area for silicide and ohmic contact formation, reducing Rb and increasing fMAX.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional integration schemes are used for HBT fabrication, then the manufacturing process is simpler, but the base resistance (Rb) increases and cut-off frequency (fMAX) decreases

Engineering Contradiction:
Improvefabrication simplicityVSAvoidbase resistance and cut-off frequency
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The extrinsic base is extended from a planar configuration into the third dimension by wrapping around the emitter structure. This vertical integration allows the extrinsic base to contact the emitter from multiple directions (top and sidewalls), effectively reducing the current path length and base resistance without increasing lateral footprint, thereby improving fMAX while maintaining fabrication feasibility

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If device scaling is pursued to improve fT/fMAX, then the device dimensions are reduced, but the collector-base capacitance (Ccb) increases

Engineering Contradiction:
Improvecut-off frequencyVSAvoidcollector-base capacitance
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The extrinsic base is nested around the emitter structure, with the intrinsic base positioned beneath the emitter and the extrinsic base wrapping around both. This nested configuration allows the bases to be closely coupled to the emitter without increasing lateral separation, reducing the collector-base capacitance while enabling smaller device dimensions for higher cut-off frequencies

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS11855195B2Transistor with wrap-around extrinsic base
Publication Date: 2023.12.26 GLOBALFOUNDRIES SINGAPORE PTE LTD
  • US11855195B2 patent drawing
  • US11855195B2 patent drawing
  • US11855195B2 patent drawing

AI summary

The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base.