F1 Interface Signaling Priority Switching Under Response Delay

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Solution Overview

Problem

The 3GPP F1 interface in 5G mobile communication systems faces challenges in timely and accurately transmitting high-priority control commands and states due to delays in signaling responses, leading to issues such as UE being offline under extreme situations.

Innovation Solution

A method and apparatus that send first process signaling to a unit, followed by second process signaling with higher priority if a response is not received, ensuring timely execution of high-priority tasks through mechanisms like incremental updating or process interruption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the system waits for a signaling response from the peer side before continuing processing, then signaling accuracy is improved, but system time delay increases

Engineering Contradiction:
Improvesignaling accuracyVSAvoidsystem time delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent introduces a time-out mechanism that initiates alternative actions (sending indication information to interrupt or notify) when the primary action (waiting for response) exceeds a predetermined time threshold. This preliminary action prevents indefinite waiting and enables the system to take corrective measures, thus resolving the contradiction between maintaining signaling accuracy and reducing time delay.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback loop where the sending end monitors whether a response is received within the time threshold. Based on this feedback (response received or not), the system dynamically adjusts its behavior: continuing normal processing if response is received, or initiating interruption/notification procedures if not received. This feedback mechanism enables the system to balance accuracy and timeliness adaptively.

Inventive Principle:
Principle #23Feedback

2Reliability

If the F1 interface transmits signaling processes sequentially waiting for responses, then signaling completeness is improved, but responsiveness to high-priority commands deteriorates

Engineering Contradiction:
Improvesignaling completenessVSAvoidresponsiveness
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent introduces dynamic adaptability to the signaling process by making the processing mode flexible based on priority and time conditions. Normal signaling processes continue sequentially, but when time-out occurs or high priority is detected, the system dynamically switches to an interrupt mode where indication information is sent to notify the peer end, allowing high-priority commands to be handled with higher responsiveness while maintaining completeness of normal signaling.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the state parameter of the signaling process from static (always waiting for response) to dynamic (can switch between waiting and interrupt modes). By introducing parameters such as time threshold, priority level, and response status, the system can adjust its behavior to prioritize speed when needed while maintaining completeness when conditions allow.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If the system implements strict waiting for all signaling responses, then control accuracy is improved, but system complexity increases

Engineering Contradiction:
Improvecontrol accuracyVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies different quality requirements to different parts of the signaling process based on their importance. Critical signaling processes that require high accuracy continue to use strict response waiting, while less critical processes can use the time-out interrupt mechanism. This local differentiation allows the system to maintain control accuracy where needed without unnecessarily increasing overall system complexity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Instead of implementing strict response waiting for all signaling processes (excessive action), the patent applies the time-out interrupt mechanism selectively based on priority and time conditions (partial action). This partial application reduces system complexity while maintaining control accuracy for critical processes, resolving the contradiction between accuracy and complexity.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12556891B2Process signaling sending method and apparatus, storage medium, and electronic device
Publication Date: 2026.02.17 ZTE CORP
  • US12556891B2 patent drawing
  • US12556891B2 patent drawing
  • US12556891B2 patent drawing

AI summary

The embodiments of the present disclosure provide a process signaling sending method and apparatus, a storage medium, and an electronic device. The method includes: sending first process signaling to a first unit, wherein the first process signaling is used for instructing the first unit to execute a first to-be-executed task; and sending, in a case where a first response message for the first process signaling is not received, second process signaling to the first unit, wherein the second process signaling is used for instructing the first unit to execute a second to-be-executed task, and a priority of the second to-be-executed task is higher than a priority of the first second to-be-executed task.